Accurate Geometric Programming-Compatible Slew Rate Modeling for Two-Stage Operational Amplifier Design Optimization

Eric J. Wyers
{"title":"Accurate Geometric Programming-Compatible Slew Rate Modeling for Two-Stage Operational Amplifier Design Optimization","authors":"Eric J. Wyers","doi":"10.1109/APCCAS55924.2022.10090335","DOIUrl":null,"url":null,"abstract":"Monomial models for the two-stage operational amplifier positive and negative slew rate performances are proposed in this work to aid the integrated circuit designer in producing optimal designs within the geometric programming design framework. Compared to the commonly-used and inaccurate slew rate design equations, the developed slew rate monomial models are capable of producing designs which have excellent slew rate performance agreement between the design optimization framework and circuit simulation, are based on highly-accurate slew rate design equations, require minimal overhead to produce, and have minimal modeling complexity with respect to the number of parameters to be estimated. We demonstrate the efficacy of the proposed slew rate models via a design test case in a standard 1.8-V, $0.18-\\mu \\mathbf{m}$ CMOS technology.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS55924.2022.10090335","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

Monomial models for the two-stage operational amplifier positive and negative slew rate performances are proposed in this work to aid the integrated circuit designer in producing optimal designs within the geometric programming design framework. Compared to the commonly-used and inaccurate slew rate design equations, the developed slew rate monomial models are capable of producing designs which have excellent slew rate performance agreement between the design optimization framework and circuit simulation, are based on highly-accurate slew rate design equations, require minimal overhead to produce, and have minimal modeling complexity with respect to the number of parameters to be estimated. We demonstrate the efficacy of the proposed slew rate models via a design test case in a standard 1.8-V, $0.18-\mu \mathbf{m}$ CMOS technology.
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精确几何规划-兼容摆率建模的两级运算放大器设计优化
本文提出了两级运算放大器正摆率和负摆率性能的单项模型,以帮助集成电路设计者在几何规划设计框架内进行优化设计。与常用的不准确的摆率设计方程相比,所开发的摆率单项模型能够产生具有良好的摆率性能的设计,设计优化框架和电路仿真之间的一致性,基于高精度的摆率设计方程,生产开销最小,建模复杂性最小,需要估计的参数数量最少。我们通过在标准1.8 v, $0.18-\mu \mathbf{m}$ CMOS技术上的设计测试案例证明了所提出的摆率模型的有效性。
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