In-Field Detection of Degradation on PCB Assembly High-Speed Buses

S. Odintsov
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引用次数: 1

Abstract

Every mission-critical system goes through extensive functionality and stress tests after being manufactured. But these tests alone do not guarantee correct system behavior in the field. A contemporary high-performance system board is a complex 3D object that may contain a few dozens of hidden layers, stacked micro-vias, high density interconnect, with all above not contributing to ease of test and reliability. Today, data transmission rates on the board may be reaching multi-gigabit ranges on a single channel. Even small changes in high-speed transmission line's impedance caused by system degradation may result in system performance issues and increased error rates due to small delays, intermittent faults and other sporadic stability issues observed in certain operation modes, at certain workloads or manifesting in a seemingly stochastic manner. Diagnosing the root cause of such faulty behavior (defects) in the field is extremely difficult. Differently from Intermittent Faults, Marginal Defects are permanent imperfections, which do not have a temporary or periodic effect. In a way, they are similar to parametric variations, pushing the system (or more specifically, the assembled board) very close or slightly beyond its specified operating margins. As a remedy, high-speed signals are normally fine-tuned or even calibrated to deliver pitch perfect timing even in case of now-ubiquitous DDR3 memories. As a negative side, the calibration mechanism may mask Marginal Defects out until the operating window shrinks to unbearable size and system starts to fail. Self-test and various built-in monitors are often used to monitor system health status, predict and prepare for possible failures. In this paper, we will present methodology aimed at overcoming described above challenges and successfully monitor high-speed data transmission interface health. The methodology is based on observation of signal sampling delays deviation and method described in the previous paper [1].
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PCB高速母线组件退化的现场检测
每个关键任务系统在制造后都要经过广泛的功能和压力测试。但是,仅靠这些测试并不能保证系统在现场的正确运行。现代高性能系统板是一个复杂的3D对象,可能包含几十个隐藏层,堆叠的微孔,高密度互连,所有这些都不利于易于测试和可靠性。今天,板上的数据传输速率可能在单个通道上达到千兆范围。在某些运行模式下,在某些工作负荷下或以看似随机的方式表现出来的小延迟、间歇性故障和其他零星的稳定性问题,即使是由系统退化引起的高速传输线阻抗的微小变化,也可能导致系统性能问题和错误率的增加。在该领域诊断这种错误行为(缺陷)的根本原因是极其困难的。与间歇性故障不同,边际缺陷是永久性缺陷,不具有暂时或周期性的影响。在某种程度上,它们类似于参数变化,推动系统(或更具体地说,组装板)非常接近或略超过其指定的操作边际。作为补救措施,高速信号通常经过微调甚至校准,即使在现在无处不在的DDR3存储器的情况下,也能提供完美的音高定时。作为消极的一面,校准机制可能会掩盖边际缺陷,直到操作窗口缩小到无法承受的大小,系统开始失效。自检和各种内置监视器通常用于监视系统健康状态,预测和准备可能的故障。在本文中,我们将介绍旨在克服上述挑战并成功监控高速数据传输接口健康的方法。该方法基于对信号采样延迟偏差的观察和先前论文[1]中描述的方法。
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