Uniformity And Reliability Of 1.5 nm Direct Tunneling Gate Oxide MOSFETs

Abstract

INTRODUCTION Direct tunneling gate oxide MOSFETs are expected to be a good possibility not only to achieve extremely high speed digital circuit operation [l] , but also to realize RF high performance for analog applications [2]. However, there are a few concerns for the use of such ultra-thin gate oxide. One is the controllability of gate oxide film thickness in terms of gate leakage current, threshold voltage, gate breakdown, etc. Another is the reliability of the oxides in terms of time-dependent breakdown and hotcarrier injection. The third is dopant penetration from gate electrode to the substrate. This paper reports for the first time experimental results respecting the film thickness control, reliahlity, and dopant penetration of the ultra-thin gate oxide. The results suggest unexpectedly good nature of such ultra-thin gate oxide films. SAMPLE FABRICATION Figure 1 shows the fabrication process flow of ultrathin gate oxide MOSFETs. The 1.5 nm gate oxide film was produced by rapid thermal oxidation (RTO). The heat flow of the RTO is shown in Fig. 2. Figure 3 shows TEM aoss section of the ultra-thin gate oxide. N+polysilicon gate doped by phosphorus was used A low sheet resistance of 1.4 m / s q was achieved for the sourceidrain extension by solid phase diffusion of phosphorus from the PSG sidewall. The CO salicide technique was also applied to 1.5 nm gate oxide MOSFETs. The resulting sheet resistance of the silicide layers is about 4 Wsq. RESULTS AND DISCUSSIONS Figure 4shows the distributions of gateleakage current (a), gate breakdown voltage (b), and threshold voltage (c) in a 6-inch wafer. The definition of the leakage current and breakdown voltage is shown in Fig. 4-(d). Despite no special care being taken to control film thickness at RTO, excellent uniformity in the distributions was confirmed. In fact, sigmas of the leakage current, breakdown voltage and Vth are 6.9, 2.5 and 1.7 %, respectively. The leakage current is very sensitive to the oxide thickness and the sigma value of 6.9 % in the leakage current of the capacitor corresponds to the oxide film thickness variation within only 0.025 nm at 3 sigma, as shown in Fig. 4-(a). This value is much better than expected. h e to the excellent gate thickness uniformity, the variations of the breakdown voltage and threshold voltage are very smal l in a wder. It should be noted that there is no A or B mode failure for the breakdown and that the threshold voltages of all the transistors are within normal range. Figure 5 shows TEM observation of the oxide film during an early stage of the RTO. Even at the veq bepnning of the oxidation at 2 seconds, good uniformity of the film was observed. Figure 6 shows the TDDB characteristics of the ultrathin gate oxide hlOSFETs in comparison with thicker gate oxide MOSFETs at 3.0 and 5.0 nm. Constant stress voltage was applied for 100 seconds and the voltage was increased with step by step as shown in Fig. 6-(a). Oxide breakdown was judged to occur when the Id-Vd curve shows leakage component as shown in the middle of Fig. 6-(b). The results shows 60 7% increase of the breakdown field compared with the 5 nm case. Ths confirms very good reliability of the ultra-thin gate oxide for breakdown. Reliability €or substrate hot-hole injection was investigated for 1.5 nm and 6.0 nm gate oxide XlOSFETs. Figure7 shows theresults. hfuch smaller thresholdvoltage shift and better subthreshold slope after the hot-carrier injection were observed in the case of 1.5 nm oxide. Thus, ultra-thin gate oxide is also very reliable in terms of TDDB and hot-carrier injection. Figure 8 shows SILK3 profiles of the gate dopant penetrations. In the case of ppol y gate, boron penetration was observed with the gate oxide thickness of at least 2.1 nm (Fig. &(a)). Thus, nitridation of the oxide would be required. To the contrary, in the case of n+poly gate, phosphorus penetration does not occur at all even with the oxide thickness of 1.5 nm (Fig. 8-(b)). These are the results of RTX at l,ooO°C for 20 seconds. Furthermore, the phosphorus penetration was not observed even at 1050°C RTA for 20 seconds (Fig. 8-(c)). In the case of furnace anneal, the phosphorus penetration does not occiu at 850°C for 30 minutes (Fig. 8-(c)). Thus, the directtunneling gate oxide can be implemented into future advanced LSI process, in terms of dopant penetration, as long as n+poly gate is used. CONCLUSIONS The uniformity, reliability and dopant penetration of 1.5 nm direct-tunneling gate oxide MOSFETs were investigated. The variation of oxide thickness in a wafer measured by gate leakage current was extraordinarily small less than 0.025nm at 3 sigma. The breakdown and threshold voltages are quite dorm. The TDDB of 1.5 nm gate oxide was found to be 60 % higher than that of 5nm gate oxide.There1iabilityfor the substrate hot-carrier injection was also improved. The dopant penetration was not observed in the n+poly gate case with RTA at 1,050"C for 20 seconds and furnace anneal at 850°C for 30minutes. These results suggestagoodmanufacturability for the 1.5 nm direct-tunneling oxide MOSFETs. REFERENCES [l] H. S. Momose et al., in IEDM Tech. Dig., p.593, 1994. [2] H. S. h4omose et al., in IEDM Tech. Dig., p. 105, 1996.