Simulation study on Z2FET scalability, process optimization and their impact on performance

Abstract

Memory technology requires high density, large volume memory arrays in the limited chip real estate. Z2FET memory architecture has demonstrated advantages for CMOS technology implementation including compatibility and scalability, novel capacitor-less memory action, area reduction, and sharp switching characteristics. As a candidate of e-DRAM applications [1-4], minimizing cell dimensions is one of the key targets in order to deliver Z2FET competitive advantage in memory technology design and applications. The cell area is mainly determined by the Z2FET length and width. Therefore, the scaling study the Z2FET length is crucial in achieving high-density storage solutions.