A unique centralized-management methodology block/architecture and a novel random input stimulus controlled variable table implementation for the latest marvell ethernet PHY UVM verification platform

Abstract

More than eighty different test environments need to be created and maintained for debugging the Marvell Ethernet PHY chip if the traditional industrial verification methodology is being used. This can easily incite very complicated debugging procedures and cause the problems and concerns of a multitude of engineering resources. The latest Marvell Ethernet PHY IC UVM verification platform integrating with the Marvell selected IP vendor's UVM library has been developed. A unique centralized-management methology block/architecture idea is brought in to build this UVM verification platform for the latest Marvell Ethernet PHY integrated circuit. All the eighty different test modes can be tested and verified in the same single UVM platform environment. This UVM verification platform environment significantly reduces the number of engineering resources needed to create and maintain the test cases. It also greatly saves debugging time and reduces chip development time. In the meanwhile, a novel random input stimulus controlled variables table idea is also implemented in this UVM verification platform to manage and improve the function coverage much more easily and efficiently.