Demonstration of Glass-based 3D Package Architectures with Embedded Dies for High Performance Computing

Abstract

This paper presents a technology demonstration of two novel 3D glass-based architectures for high performance computing applications. Current 3D technologies are limited by Through Silicon Vias (TSVs), and the proposed approached based on Glass Panel Embedding (GPE) eliminates TSVs resulting in a more robust 3D packaging platform that supports a variety of architectures. Two such architectures are designed and demonstrated in this paper. The first test vehicle shows multiple dies embedded and interconnected in a glass cavity, along with dies assembled on top using a microbump interface. The second test vehicle shows a 50x50 mm glass interposer package with 4 dies embedded in the core, 8 HBM emulators & 2 large SoCs assembled on top at 35 micron-bump pitch.