Measurement of supply noise suppression by substrate and deep N-well in 90nm process

Abstract

This paper measures and compares power supply and ground noises in a triple-well structure and a twin-well stricture. The measurement results of power supply and ground waveforms in a 90 nm CMOS process reveal that the power noise reduction thanks to the increased junction capacitance associated with the triple-well structure overwhelms the ground noise suppression due to the resistive network of p-substrate in the twin-well structure. These noise suppression effects are well correlated with the simulation that uses on-chip RC power distribution model with package inductance, chip-level p-substrate resistive mesh and distributed well junction capacitances.