Concurrent fault tolerant control of semiconductor measurement and testing

Abstract

Fault tolerant modeling constraints are presented to reduce wafer test times attributed to sequential semiconductor measurement and testing (SMT) and to avoid product damage and deviation in quality during testing. The concept is expressed using the Unified Modeling Language statecharts and is further reinforced with a mathematical finite-state machine. By adhering to constraints, translation of this object-oriented model to the solution space has been successfully applied to a parametric in-line testing system (PITS) resulting in significant reduction of test time. PITS statistical data is used to support our models by comparing previous sequential implementation to our new concurrent approach.