Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962993
G. Gaxiola, L. Hennessy
As the industry prepares for more realistic automated material handling intrabay designs it is becoming necessary to make decisions about feasible configurations of the layouts that are going to be used One of the questions that still remains unanswered, that is addressed in this paper, is the level of interconnectivity among the different bays through the intrabay automated material handling system. This paper summarizes a study that compares three different options for intrabay layouts and provides conclusions based on results from static and dynamic analysis. The three options were evaluated based on the impact each one of them has on total distance traveled by the lots, average delivery and transport times, vehicle counts and equipment set.
{"title":"Evaluation of advantages of integrating 300 mm AMHS fab layouts in the photo area","authors":"G. Gaxiola, L. Hennessy","doi":"10.1109/ISSM.2001.962993","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962993","url":null,"abstract":"As the industry prepares for more realistic automated material handling intrabay designs it is becoming necessary to make decisions about feasible configurations of the layouts that are going to be used One of the questions that still remains unanswered, that is addressed in this paper, is the level of interconnectivity among the different bays through the intrabay automated material handling system. This paper summarizes a study that compares three different options for intrabay layouts and provides conclusions based on results from static and dynamic analysis. The three options were evaluated based on the impact each one of them has on total distance traveled by the lots, average delivery and transport times, vehicle counts and equipment set.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121821462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962930
T. Yao, T. Hiraike, K. Kobayashi, S. Asai, I. Hanyu
Line width control is a key factor in LSI manufacturing. This paper describes the relationship between line width uniformity and the illumination system of an exposure tool. Variation in the local value of partial coherence a is the cause of the optical proximity effect (OPE) variation across the image field of an exposure tool. By quantifying partial coherence /spl sigma/ and decreasing a variation, OPE variation within the image field was improved from 21.2 nm to 8.8 nm. We reduced OPE variation among tools by setting up these tools with agreeing a values. This paper also discusses the effect of illumination source uniformity on line width. Nonuniformity of an illumination source induces a line width difference between pair lines. We improved the treatment for these problems by adjusting the illumination source uniformity.
{"title":"Improvement of CD uniformity in 180 nm LSI manufacturing by optimizing illumination system","authors":"T. Yao, T. Hiraike, K. Kobayashi, S. Asai, I. Hanyu","doi":"10.1109/ISSM.2001.962930","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962930","url":null,"abstract":"Line width control is a key factor in LSI manufacturing. This paper describes the relationship between line width uniformity and the illumination system of an exposure tool. Variation in the local value of partial coherence a is the cause of the optical proximity effect (OPE) variation across the image field of an exposure tool. By quantifying partial coherence /spl sigma/ and decreasing a variation, OPE variation within the image field was improved from 21.2 nm to 8.8 nm. We reduced OPE variation among tools by setting up these tools with agreeing a values. This paper also discusses the effect of illumination source uniformity on line width. Nonuniformity of an illumination source induces a line width difference between pair lines. We improved the treatment for these problems by adjusting the illumination source uniformity.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"327 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123305178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962954
Y. Inagaki, M. Shimizu
Buffered HF (BHF), which is a mixture of hydrofluoric acid and ammonium fluoride, is used for etching and cleaning silicon wafers. Waste BHF is generally treated with a variety of chemicals, resulting in the discharge of much wastewater and sludge. We have developed a new method to extend the period of BHF can be used by supplying elements which depend on the ratio of NH/sub 4/F to HF in BHF. This method can reduce the BHF required, reduce the chemicals required to treat waste BHF and decrease the discharge of wastewater and sludge.
{"title":"Resource conservation of buffered HF in semiconductor manufacturing","authors":"Y. Inagaki, M. Shimizu","doi":"10.1109/ISSM.2001.962954","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962954","url":null,"abstract":"Buffered HF (BHF), which is a mixture of hydrofluoric acid and ammonium fluoride, is used for etching and cleaning silicon wafers. Waste BHF is generally treated with a variety of chemicals, resulting in the discharge of much wastewater and sludge. We have developed a new method to extend the period of BHF can be used by supplying elements which depend on the ratio of NH/sub 4/F to HF in BHF. This method can reduce the BHF required, reduce the chemicals required to treat waste BHF and decrease the discharge of wastewater and sludge.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114428680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963024
S. Y. Ku, T. Lo, Y. Shih, C. Shi, C.H. Wang, Y.J. Yu
Pre-metal clean is a critical procedure before the metal loop in the salicide process. Surface defects such as the surface native oxide or any other contamination may result in a poor adhesion of Ti/TiN, for example, and hence the poor salicide formation. HF treatment with IPA dry is a widely used methodology for surface defect removal, and results in a clean surface which is water spot free and has less chemical oxide. However, a cluster type defect is an accompaniment of this treatment in the salicide process. The aim of this work is to provide an optimized cleaning procedure at pre-metal clean for mass production.
{"title":"Pre-metal clean optimization for cluster defect prevention","authors":"S. Y. Ku, T. Lo, Y. Shih, C. Shi, C.H. Wang, Y.J. Yu","doi":"10.1109/ISSM.2001.963024","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963024","url":null,"abstract":"Pre-metal clean is a critical procedure before the metal loop in the salicide process. Surface defects such as the surface native oxide or any other contamination may result in a poor adhesion of Ti/TiN, for example, and hence the poor salicide formation. HF treatment with IPA dry is a widely used methodology for surface defect removal, and results in a clean surface which is water spot free and has less chemical oxide. However, a cluster type defect is an accompaniment of this treatment in the salicide process. The aim of this work is to provide an optimized cleaning procedure at pre-metal clean for mass production.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117105383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962938
Y. Kawashima, T. Ichikawa, N. Nakamura, B. Kawano, T. Ide, S. Obata, Y. Den, M. Kudo
The optimum conditions of a fluorinated silica glass/SiO/sub 2/ (FSG/SiO/sub 2/) interlayer were investigated for preventing Al-wiring delamination. TiF/sub x/ formation by F atoms transported from the FSG film to the Ti/SiO/sub 2/ interface during the metallization process induced the delamination. Correlation between the Al-wiring delamination and F concentration at Ti/SiO/sub 2/ was demonstrated by a 3-D mapping of F concentrations at Ti/SiO/sub 2/ with various thickness of SiO/sub 2/ film and F content in the FSG film. Some treatments of the FSG/SiO/sub 2/ interlayer to reduce F accumulation at Ti/SiO/sub 2/ were also examined. It was revealed that more than 4500-/spl Aring/ thickness and strain relaxation of the compressive SiO/sub 2/ film were effective for F reduction at Ti/SiO/sub 2/. On the other hand, F concentration at Ti/SiO/sub 2/ was independent of F content in the FSG film in the range of 2-5 %. F content in FSG film should be kept as much as possible, that is, 4-5 % not to increase the capacitance between adjacent metal lines. The Al-wiring delamination was prevented by introducing these parameters of the FSG/SiO/sub 2/ interlayer into the fabrication line.
{"title":"Control of FSG/SiO/sub 2/ interlayer conditions to prevent Al-wiring delamination caused by F accumulation at Ti/SiO/sub 2/","authors":"Y. Kawashima, T. Ichikawa, N. Nakamura, B. Kawano, T. Ide, S. Obata, Y. Den, M. Kudo","doi":"10.1109/ISSM.2001.962938","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962938","url":null,"abstract":"The optimum conditions of a fluorinated silica glass/SiO/sub 2/ (FSG/SiO/sub 2/) interlayer were investigated for preventing Al-wiring delamination. TiF/sub x/ formation by F atoms transported from the FSG film to the Ti/SiO/sub 2/ interface during the metallization process induced the delamination. Correlation between the Al-wiring delamination and F concentration at Ti/SiO/sub 2/ was demonstrated by a 3-D mapping of F concentrations at Ti/SiO/sub 2/ with various thickness of SiO/sub 2/ film and F content in the FSG film. Some treatments of the FSG/SiO/sub 2/ interlayer to reduce F accumulation at Ti/SiO/sub 2/ were also examined. It was revealed that more than 4500-/spl Aring/ thickness and strain relaxation of the compressive SiO/sub 2/ film were effective for F reduction at Ti/SiO/sub 2/. On the other hand, F concentration at Ti/SiO/sub 2/ was independent of F content in the FSG film in the range of 2-5 %. F content in FSG film should be kept as much as possible, that is, 4-5 % not to increase the capacitance between adjacent metal lines. The Al-wiring delamination was prevented by introducing these parameters of the FSG/SiO/sub 2/ interlayer into the fabrication line.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129555043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962927
T. Shibata, K. Sugoruo, K. Sughihara, K. Okumura, T. Nishihashi, K. Kashimoto, J. Fujiyama, Y. Sakurada, T. Gorou, N. Saji, M. Tsunoda
A new type of ion implanter developed for an agile fab can eliminate the processes concerned with photo resist lithography from the ion implantation process. This new ion implantation technology can reduce the row process time, footprint, and the cost of ownership to less than 1/2 that of conventional ion implantation technology. We are making further developments on this ion implanter and evaluating technical issues related to ion implantation, a technique suitable for manufacturing submicron IC devices. Based on the results of evaluating the prototype machine, we will produce the next /spl beta/-machine.
{"title":"Lithography-less ion implantation technology for agile fab","authors":"T. Shibata, K. Sugoruo, K. Sughihara, K. Okumura, T. Nishihashi, K. Kashimoto, J. Fujiyama, Y. Sakurada, T. Gorou, N. Saji, M. Tsunoda","doi":"10.1109/ISSM.2001.962927","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962927","url":null,"abstract":"A new type of ion implanter developed for an agile fab can eliminate the processes concerned with photo resist lithography from the ion implantation process. This new ion implantation technology can reduce the row process time, footprint, and the cost of ownership to less than 1/2 that of conventional ion implantation technology. We are making further developments on this ion implanter and evaluating technical issues related to ion implantation, a technique suitable for manufacturing submicron IC devices. Based on the results of evaluating the prototype machine, we will produce the next /spl beta/-machine.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128970266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962965
W. Shindo, S. Sugimoto, R. Makara, Puttachai Rattanalangkan, R. Lui
A methodology to enhance baseline yield by utilizing fail bitmap (FBM) analysis is presented in this paper. Yield impact of each process step is estimated from FBM-defect correlation and FBM classification. Statistical accuracy of the data is evaluated by using actual wafer-to-wafer variation of our fab, and is significantly improved by increasing FBM sample size. In order to analyze a large amount of data in real-time manner, throughput of the data analysis is also enhanced by an automated system for timely data feedback to yield enhancement activities.
{"title":"Acceleration of yield enhancement activity by utilizing real-time fail bitmap analysis","authors":"W. Shindo, S. Sugimoto, R. Makara, Puttachai Rattanalangkan, R. Lui","doi":"10.1109/ISSM.2001.962965","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962965","url":null,"abstract":"A methodology to enhance baseline yield by utilizing fail bitmap (FBM) analysis is presented in this paper. Yield impact of each process step is estimated from FBM-defect correlation and FBM classification. Statistical accuracy of the data is evaluated by using actual wafer-to-wafer variation of our fab, and is significantly improved by increasing FBM sample size. In order to analyze a large amount of data in real-time manner, throughput of the data analysis is also enhanced by an automated system for timely data feedback to yield enhancement activities.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130487731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962950
D. Wollstein, J. Raebiger, S. Lingel
Presents three independent run-to-run APC controllers for the chemical-mechanical polishing (CMP). The controllers are applied to oxide polish processes in AMD's Fab30 to improve (a) the lot-to-lot variation, (b) to reduce the wafer-to-wafer variation and (c) to increase the wafer uniformity of the post-polish oxide thickness. Since different products and layers are processed on the same tools a method was introduced to compensate device and layer dependencies. The control algorithms were extended to a bi-layered polish process. Significant improvement was achieved for the individual controllers applied in the high volume production environment of Fab30 under the condition of a permanently changing product mix.
{"title":"Multiple objective APC application for an oxide CMP process in a high volume production environment","authors":"D. Wollstein, J. Raebiger, S. Lingel","doi":"10.1109/ISSM.2001.962950","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962950","url":null,"abstract":"Presents three independent run-to-run APC controllers for the chemical-mechanical polishing (CMP). The controllers are applied to oxide polish processes in AMD's Fab30 to improve (a) the lot-to-lot variation, (b) to reduce the wafer-to-wafer variation and (c) to increase the wafer uniformity of the post-polish oxide thickness. Since different products and layers are processed on the same tools a method was introduced to compensate device and layer dependencies. The control algorithms were extended to a bi-layered polish process. Significant improvement was achieved for the individual controllers applied in the high volume production environment of Fab30 under the condition of a permanently changing product mix.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126409909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962956
S. Noda, M. Miyamoto, H. Horibe, I. Oya, M. Kuzumoto, T. Kataoka
A resist stripping process using highly-concentrated ozone gas and water vapor has been developed This method features higher removal rate and/or an eco-friendly process, compared with conventional methods. Influences of substrate temperature, water vapor concentration, anti residence time, on the removal rate have been experimentally investigated in detail. An FT-IR spectroscope was used to analyze the substrate before/after the treatment in order to clarify the mechanism of the resist stripping by ozone and water vapor It is shown that water plays an important role in the resist decomposition. Main factor of higher removal rate over 1 /spl mu/m/min in this method is also discussed.
{"title":"Development of photo-resist stripping process using ozone and water vapor","authors":"S. Noda, M. Miyamoto, H. Horibe, I. Oya, M. Kuzumoto, T. Kataoka","doi":"10.1109/ISSM.2001.962956","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962956","url":null,"abstract":"A resist stripping process using highly-concentrated ozone gas and water vapor has been developed This method features higher removal rate and/or an eco-friendly process, compared with conventional methods. Influences of substrate temperature, water vapor concentration, anti residence time, on the removal rate have been experimentally investigated in detail. An FT-IR spectroscope was used to analyze the substrate before/after the treatment in order to clarify the mechanism of the resist stripping by ozone and water vapor It is shown that water plays an important role in the resist decomposition. Main factor of higher removal rate over 1 /spl mu/m/min in this method is also discussed.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125575722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962923
F. Sadjadi, T. Baker
Manufacturing cycle time at AMD's Fab25 Austin, Texas facility has improved from the bottom third to the top of Sematech's cycle time per mask layer metric list. Steady improvement in cycle time performance has been attained in the midst of a steep ramp from 0.25 /spl mu/m to 0.18 /spl mu/m technology. This paper explains the fundamental changes that were made to accomplish these improvements and evaluate their impact upon Fab25's cycle time reduction efforts. Focus areas of interest are: philosophy and behavior, modeling, dispatching, planning, and operations.
{"title":"Comprehensive cycle time reduction program at AMD's fab25","authors":"F. Sadjadi, T. Baker","doi":"10.1109/ISSM.2001.962923","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962923","url":null,"abstract":"Manufacturing cycle time at AMD's Fab25 Austin, Texas facility has improved from the bottom third to the top of Sematech's cycle time per mask layer metric list. Steady improvement in cycle time performance has been attained in the midst of a steep ramp from 0.25 /spl mu/m to 0.18 /spl mu/m technology. This paper explains the fundamental changes that were made to accomplish these improvements and evaluate their impact upon Fab25's cycle time reduction efforts. Focus areas of interest are: philosophy and behavior, modeling, dispatching, planning, and operations.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128181955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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