{"title":"Low cost partial scan design: a high level synthesis approach","authors":"M. Flottes, R. Pires, B. Rouzeyre, L. Volpe","doi":"10.1109/VTEST.1998.670887","DOIUrl":null,"url":null,"abstract":"In this paper, we present a high level synthesis method for partial scan designs. High level testability information are used to guide the synthesis process towards designs with a minimal number of scan registers. The maximal fault coverage is achievable for these designs. This method mainly leans on ad-hoc modifications of the register allocation process.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1998.670887","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this paper, we present a high level synthesis method for partial scan designs. High level testability information are used to guide the synthesis process towards designs with a minimal number of scan registers. The maximal fault coverage is achievable for these designs. This method mainly leans on ad-hoc modifications of the register allocation process.
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