ESD qualification and testing of semiconductor electronic components

Abstract

Electrostatic discharge (ESD) standards, qualification and testing techniques are not keeping pace with the wide proliferation of product and package types, chip architectures, digital/analog mixed signal applications, multichip module (MCM) packages, and three-dimensional silicon packages. ESD test standards are primarily focused on impulse wave forms and testers and are not addressing the pace and changing trend of the semiconductor industry. For example, most ESD event simulators are not adequately addressing product with high pin counts, high-volume testing, and software needs. This paper discusses our perspective of those adjustments needed to drive ESD learning on product chips and of new package environments. Also discussed are ESD testing methodologies, wafer-level test systems, packaging effects, simulation, and MCM ESD testing.