Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550813
Jong-Kai Lin, J. Drye, W. Lytle, T. Scharr, R. Subrahmanyan, Ranjan Sharma
Conductive polymer bonded flip chip interconnect systems can provide an attractive alternative flip chip technology in terms of cost and manufacturability. This work examines the feasibility of application of such a technology. A mathematical model for stencil printing of conductive adhesive paste is developed to demonstrate some of the factors affecting the print quality. Designed experiments is used to optimize bump dimensional uniformity. The electrical performance of conductive polymer flip chip interconnects is evaluated through both GaAs and Si devices. The microwave insertion loss (S/sub 21/) of a coplanar waveguide test vehicle showed a loss rate of 0.031 dB/GHz for non-underfilled flip chip assembly and 0.065 dB/GHz for those with underfill encapsulation. These S/sub 21/ data are almost identical to a device with same test structure and a Au ball bumped flip chip assembly. Additional test using a CT-2 antenna switch GaAs device flip chip bonded on a FR4 board showed an identical performance (up to 2 GHz frequency) to the same assembly using Au-Sn eutectic bumps. Reliability of conductive polymer bumps was evaluated using Si die flip chip bonded on FR4 substrates. Results showed no failures on temperature cycle, humidity, vibration, and mechanical shock tests. There were 8.6% failures on HAST and 6% failures on thermal shock tests on test conditions stated in the text.
{"title":"Conductive polymer bump interconnects","authors":"Jong-Kai Lin, J. Drye, W. Lytle, T. Scharr, R. Subrahmanyan, Ranjan Sharma","doi":"10.1109/ECTC.1996.550813","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550813","url":null,"abstract":"Conductive polymer bonded flip chip interconnect systems can provide an attractive alternative flip chip technology in terms of cost and manufacturability. This work examines the feasibility of application of such a technology. A mathematical model for stencil printing of conductive adhesive paste is developed to demonstrate some of the factors affecting the print quality. Designed experiments is used to optimize bump dimensional uniformity. The electrical performance of conductive polymer flip chip interconnects is evaluated through both GaAs and Si devices. The microwave insertion loss (S/sub 21/) of a coplanar waveguide test vehicle showed a loss rate of 0.031 dB/GHz for non-underfilled flip chip assembly and 0.065 dB/GHz for those with underfill encapsulation. These S/sub 21/ data are almost identical to a device with same test structure and a Au ball bumped flip chip assembly. Additional test using a CT-2 antenna switch GaAs device flip chip bonded on a FR4 board showed an identical performance (up to 2 GHz frequency) to the same assembly using Au-Sn eutectic bumps. Reliability of conductive polymer bumps was evaluated using Si die flip chip bonded on FR4 substrates. Results showed no failures on temperature cycle, humidity, vibration, and mechanical shock tests. There were 8.6% failures on HAST and 6% failures on thermal shock tests on test conditions stated in the text.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115406196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517452
S. Huang
The thermal impedance is an important parameter for a semiconductor laser, especially for a pump laser diode where a high current is needed to drive the laser to achieve the required performance. A precise measurement of thermal impedance is needed to characterize the thermal effect on the laser and to diagnose the thermal path on the laser packaging. Traditional measurements for the thermal impedance involve pulsing or modulating the lasers. Here, for the first time we used a complete optical method without electrical pulsation or modulation. The double mode spectra of fiber grating lasers were used to measure the thermal impedance of a semiconductor laser with accuracy not obtainable by other methods.
{"title":"Accurate thermal impedance measurement for semiconductor lasers by the double modes of fiber grating lasers","authors":"S. Huang","doi":"10.1109/ECTC.1996.517452","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517452","url":null,"abstract":"The thermal impedance is an important parameter for a semiconductor laser, especially for a pump laser diode where a high current is needed to drive the laser to achieve the required performance. A precise measurement of thermal impedance is needed to characterize the thermal effect on the laser and to diagnose the thermal path on the laser packaging. Traditional measurements for the thermal impedance involve pulsing or modulating the lasers. Here, for the first time we used a complete optical method without electrical pulsation or modulation. The double mode spectra of fiber grating lasers were used to measure the thermal impedance of a semiconductor laser with accuracy not obtainable by other methods.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115599975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517462
A. Domadia, D. Mendoza
The general construction of the TBGA developed at LSI Logic Corp. is discussed. Ground/power plane connections are typically provided in double metal tape for Tape Ball Grid Array (TBGA) by using plated vias for connections. A unique process which allows ground connections for TBGA package in assembly, rather than in tape is discussed. It further discusses a novel way to provide power plane connections also during assembly of a TBGA package, instead of providing it in the tape. Providing such interconnections in the assembly makes the product more cost effective and TBGA tape becomes more manufacturable. Both equipment and process for this unique "down bond" technique are discussed. Such an interconnection technique is currently being used in manufacturing at LSI Logic Corp.
{"title":"TBGA bond process for ground and power plane connections","authors":"A. Domadia, D. Mendoza","doi":"10.1109/ECTC.1996.517462","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517462","url":null,"abstract":"The general construction of the TBGA developed at LSI Logic Corp. is discussed. Ground/power plane connections are typically provided in double metal tape for Tape Ball Grid Array (TBGA) by using plated vias for connections. A unique process which allows ground connections for TBGA package in assembly, rather than in tape is discussed. It further discusses a novel way to provide power plane connections also during assembly of a TBGA package, instead of providing it in the tape. Providing such interconnections in the assembly makes the product more cost effective and TBGA tape becomes more manufacturable. Both equipment and process for this unique \"down bond\" technique are discussed. Such an interconnection technique is currently being used in manufacturing at LSI Logic Corp.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124284852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550510
A. Kuo, W.T. Chen, L. Nguyen, K. Chen, G. Slenski
Moisture-induced cracking during solder reflow is a critical reliability problem with plastic-encapsulated microcircuits (PEMs). Such cracking, referred to as "popcorning" occurs from the evaporation and expansion of moisture absorbed by the molding compound. This is the third in a series of papers from a DoD-funded project to provide an expert system for design of PEMs. This study is aimed at establishing a rule-based system to address reliability problems related to popcorning such as interfacial delamination, mold compound moisture sensitivity, and mold compound fracture toughness. This paper addresses the fracture mechanics aspects of popcoming, and more specifically, the propensity of some packages to popcorn than others. The physics of why a TSOP-32 lead package is more susceptible to moisture cracking than a PQFP-52 lead package of the same packaging materials is explained in this paper.
{"title":"Popcorning-a fracture mechanics approach","authors":"A. Kuo, W.T. Chen, L. Nguyen, K. Chen, G. Slenski","doi":"10.1109/ECTC.1996.550510","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550510","url":null,"abstract":"Moisture-induced cracking during solder reflow is a critical reliability problem with plastic-encapsulated microcircuits (PEMs). Such cracking, referred to as \"popcorning\" occurs from the evaporation and expansion of moisture absorbed by the molding compound. This is the third in a series of papers from a DoD-funded project to provide an expert system for design of PEMs. This study is aimed at establishing a rule-based system to address reliability problems related to popcorning such as interfacial delamination, mold compound moisture sensitivity, and mold compound fracture toughness. This paper addresses the fracture mechanics aspects of popcoming, and more specifically, the propensity of some packages to popcorn than others. The physics of why a TSOP-32 lead package is more susceptible to moisture cracking than a PQFP-52 lead package of the same packaging materials is explained in this paper.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116711558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550880
Hong Yang, P. Deane, P. Magill, K. Murty
As part of an investigation of using eutectic 96.5Sn-3.5Ag solder for flip chip interconnection, this paper presents the results on mechanical characterization of 96.5Sn-3.5Ag eutectic solder and solder joints. Constant-load creep tests of 96.5Sn-3.5Ag solder alloy were performed at high homologous temperatures from 25/spl deg/C to 180/spl deg/C. Single lap shear tests were performed on joined flip chip packages with an area array of 96.5Sn-3.5Ag solder bumps-33/spl times/33 bumps per chip. Tensile creep tests were performed on bulk 96.5Sn-3.5Ag solder specimens. The steady-state strain-rates span 7 orders of magnitude ranging from 10/sup -9/ to 10/sup -2/ (1/s). The apparent activation energy for creep was found to be 0.57 ev. The stress exponent in the power-law creep equation is /spl ap/10 which is unusually high compared to that of many other metals. The underlying controlling mechanisms is identified as low-temperature dislocation climb.
{"title":"Creep deformation of 96.5Sn-3.5Ag solder joints in a flip chip package","authors":"Hong Yang, P. Deane, P. Magill, K. Murty","doi":"10.1109/ECTC.1996.550880","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550880","url":null,"abstract":"As part of an investigation of using eutectic 96.5Sn-3.5Ag solder for flip chip interconnection, this paper presents the results on mechanical characterization of 96.5Sn-3.5Ag eutectic solder and solder joints. Constant-load creep tests of 96.5Sn-3.5Ag solder alloy were performed at high homologous temperatures from 25/spl deg/C to 180/spl deg/C. Single lap shear tests were performed on joined flip chip packages with an area array of 96.5Sn-3.5Ag solder bumps-33/spl times/33 bumps per chip. Tensile creep tests were performed on bulk 96.5Sn-3.5Ag solder specimens. The steady-state strain-rates span 7 orders of magnitude ranging from 10/sup -9/ to 10/sup -2/ (1/s). The apparent activation energy for creep was found to be 0.57 ev. The stress exponent in the power-law creep equation is /spl ap/10 which is unusually high compared to that of many other metals. The underlying controlling mechanisms is identified as low-temperature dislocation climb.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121056763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.551421
S. Greer
An evaporated, extended eutectic (E-3) bump structure has been defined. This positive standoff Pb/Sn solder bump builds on the evaporative structure used to produce C-4 interconnects but utilizes a thicker Sn cap to provide a low temperature, eutectic joining medium for flip chip on board (FCOB) applications. It has been shown that this new structure can be adapted to existing FCOB methodologies without altering the tools or processes being used today. By providing eutectic melting right on the bump itself, direct joining to organic assemblies is achieved without special processing at the board level. This leads directly to cost reductions and improved wirability at assembly. These options are illustrated. The characteristics of the bump have been evaluated and reliability data has demonstrated that this bump performs as well as or better than other solder interconnect structures. Extension of this joining technology to ceramics substrates has also been demonstrated.
{"title":"Am extended eutectic solder bump for FCOB","authors":"S. Greer","doi":"10.1109/ECTC.1996.551421","DOIUrl":"https://doi.org/10.1109/ECTC.1996.551421","url":null,"abstract":"An evaporated, extended eutectic (E-3) bump structure has been defined. This positive standoff Pb/Sn solder bump builds on the evaporative structure used to produce C-4 interconnects but utilizes a thicker Sn cap to provide a low temperature, eutectic joining medium for flip chip on board (FCOB) applications. It has been shown that this new structure can be adapted to existing FCOB methodologies without altering the tools or processes being used today. By providing eutectic melting right on the bump itself, direct joining to organic assemblies is achieved without special processing at the board level. This leads directly to cost reductions and improved wirability at assembly. These options are illustrated. The characteristics of the bump have been evaluated and reliability data has demonstrated that this bump performs as well as or better than other solder interconnect structures. Extension of this joining technology to ceramics substrates has also been demonstrated.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125959382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517388
F. Christiaens, E. Beyne
This paper deals with transient thermal modelling and characterisation of packaged semiconductor devices. The investigated semiconductor device is a hybrid thermal test structure consisting of a small thermal test chip bonded to a ceramic substrate. The dynamic thermal behaviour of this structure has been studied numerically and experimentally. Temperature step responses were calculated by means of finite element analysis. The impact of the die, die attach, and substrate material on the thermal impedance is presented. A compact model comprising lumped thermal resistances and capacitances is synthesised from the numerical step response data. In addition, thermal impedance measurements were performed on a hybrid thermal test vehicle. This study shows that transient thermal impedance measurements provide much more physical information about the internal heat flow path than steady-state thermal resistance measurements.
{"title":"Transient thermal modeling and characterization of a hybrid component","authors":"F. Christiaens, E. Beyne","doi":"10.1109/ECTC.1996.517388","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517388","url":null,"abstract":"This paper deals with transient thermal modelling and characterisation of packaged semiconductor devices. The investigated semiconductor device is a hybrid thermal test structure consisting of a small thermal test chip bonded to a ceramic substrate. The dynamic thermal behaviour of this structure has been studied numerically and experimentally. Temperature step responses were calculated by means of finite element analysis. The impact of the die, die attach, and substrate material on the thermal impedance is presented. A compact model comprising lumped thermal resistances and capacitances is synthesised from the numerical step response data. In addition, thermal impedance measurements were performed on a hybrid thermal test vehicle. This study shows that transient thermal impedance measurements provide much more physical information about the internal heat flow path than steady-state thermal resistance measurements.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123559413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517427
H. Katzier, B. Keller, P. Pagnin
We present the results of a field-based 3D time domain simulation of a new board connector. The connector is a high pincount SpeedPac(R) connector with four rows providing 136 high frequency twinax chambers per 100 mm. The results of the field simulation are the near- and far-end crosstalk, the reflection and transmission characteristics in the time and frequency domain. For the field simulation we use the program package MAFIA(R), which is based on the Finite-Integration-Technique (FIT). We also present results obtained from a reliable SPICE model of the SpeedPac(R) connector. By means of typical measurements and simulation results the reliability of the SPICE(R)-Model is demonstrated. All important electrical characteristics of the connector can be simulated by the SPICE(R)-Model. The comparison between the field simulation, the SPICE(R)-simulation and measurement is very good up to a limit of f=4 GHz and risetimes of tr>50 ps.
{"title":"Field-based design of a new high pincount board connector for high data rate transmission","authors":"H. Katzier, B. Keller, P. Pagnin","doi":"10.1109/ECTC.1996.517427","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517427","url":null,"abstract":"We present the results of a field-based 3D time domain simulation of a new board connector. The connector is a high pincount SpeedPac(R) connector with four rows providing 136 high frequency twinax chambers per 100 mm. The results of the field simulation are the near- and far-end crosstalk, the reflection and transmission characteristics in the time and frequency domain. For the field simulation we use the program package MAFIA(R), which is based on the Finite-Integration-Technique (FIT). We also present results obtained from a reliable SPICE model of the SpeedPac(R) connector. By means of typical measurements and simulation results the reliability of the SPICE(R)-Model is demonstrated. All important electrical characteristics of the connector can be simulated by the SPICE(R)-Model. The comparison between the field simulation, the SPICE(R)-simulation and measurement is very good up to a limit of f=4 GHz and risetimes of tr>50 ps.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116434817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550759
S.C. Wang, C. Wang, Y. Tu, C. J. Hwang, S. Chi, W.H. Wang, Wei Cheng
The effect of Au coating on the joint strength, weld width, and penetration depth in laser welding technique for Invar-Invar packages is investigated experimentally. It is found that the joint strength, weld width, and penetration depth in the welded joints are strongly dependent on the Au thickness on the Invar material. The Invar-Invar joints with thick Au coating show narrower weld width, shallower penetration, and hence less joint strength than those of the package with thin Au coating. The increase in both the thermal conductivity and the vapor volume in the welded joints as the coating of Au thickness increases are the possible mechanisms for reduction of the weld width, penetration depth, and hence the joint strength. To the best of the authors' knowledge, this development of a new Invar-Invar package which combines the Au coating with laser welding technique has not been published yet.
{"title":"Effect of Au coating on joint strength in laser welding for Invar-Invar packages","authors":"S.C. Wang, C. Wang, Y. Tu, C. J. Hwang, S. Chi, W.H. Wang, Wei Cheng","doi":"10.1109/ECTC.1996.550759","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550759","url":null,"abstract":"The effect of Au coating on the joint strength, weld width, and penetration depth in laser welding technique for Invar-Invar packages is investigated experimentally. It is found that the joint strength, weld width, and penetration depth in the welded joints are strongly dependent on the Au thickness on the Invar material. The Invar-Invar joints with thick Au coating show narrower weld width, shallower penetration, and hence less joint strength than those of the package with thin Au coating. The increase in both the thermal conductivity and the vapor volume in the welded joints as the coating of Au thickness increases are the possible mechanisms for reduction of the weld width, penetration depth, and hence the joint strength. To the best of the authors' knowledge, this development of a new Invar-Invar package which combines the Au coating with laser welding technique has not been published yet.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124659448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550515
G. Aguirre, A. Cangellaris, M. Pasik
Presents preliminary results for a new way of addressing radiated emissions from packaged electronic systems. We have validated the FDTD methodology for determining the peak radiation frequencies for a simple microstrip transmission line structure. Also, we have demonstrated the impact of placing ground pins between the signal and absolute ground planes on the radiation characteristics of a microstrip line capacitively coupled to an absolute ground. The placement and location of grounding pins is critical to the reduction of EMI.
{"title":"Numerical investigation of radiated emissions mechanisms in single-chip packages","authors":"G. Aguirre, A. Cangellaris, M. Pasik","doi":"10.1109/ECTC.1996.550515","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550515","url":null,"abstract":"Presents preliminary results for a new way of addressing radiated emissions from packaged electronic systems. We have validated the FDTD methodology for determining the peak radiation frequencies for a simple microstrip transmission line structure. Also, we have demonstrated the impact of placing ground pins between the signal and absolute ground planes on the radiation characteristics of a microstrip line capacitively coupled to an absolute ground. The placement and location of grounding pins is critical to the reduction of EMI.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129536669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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