Modeling the fringe capacitance of multilevel VLSI interconnects

Abstract

Summary form only given. An analytical model for the fringing capacitance is described based on the work of C.-D. Yuan and T. Trick (IEEE Electron Device Lett. vol. EDL-3, p.391-3, 1982) that closely approximates the electric-field configuration at the edges of the line. The author extends this previous work by including in the model the effect of crossing wiring levels and adjacent lines. The model is based on the physics of electric field and therefore is not limited to a specific interconnect technology. It has been used to determine the extent of fringing in various configuration and the point at which adjacent lines modify the fringing capacitance. The equations in the model for the fringing capacitance are not complex and are well suited for interactive CAD applications. Comparison of the results of the analytical model to numerical simulations has shown good agreement over a broad range of dimensions, typically within 15% for separations to crossing levels and adjacent lines down to 1.0 mu m.<>