Special session 12B: Panel post-silicon validation & test in huge variance era

Takahiro J. Yamaguchi, J. Abraham, G. Roberts, S. Natarajan, D. Ciplickas
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引用次数: 1

Abstract

At the 1999 ITC, Pat Gelsinger from Intel delivered an important keynote address where he outlined the need for a low-pin count tester with lower performance pin electronics to meet the stringent test cost requirements of a billion transistor machine. At the 2009 ITC, engineers from AMD came forward with an I/O test solution that is believed to meet the Intel challenge using a cash-resident self-testing strategy combined with an external low-pin count tester. How can we drive major challenges to post-silicon validation and in huge variance era? Technology scaling enables us to trade off amplitude resolution for time resolution. Accordingly, both internal and external tests, some of which use low-pin count testers, are also shifting from voltage centric tests to timing centric tests. How can time resolution be used to push the timing centric tests beyond current limitations? How can spatial resolution be realized to enhance yields in terms of both die-to-die variations and within-die variations? What is necessary to provide robust on-chip solutions subject to huge variations, which may be combined with an external low-pin count tester?
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专场12B:大方差时代的面板后硅验证与测试
在1999年的ITC上,来自英特尔的Pat Gelsinger发表了一个重要的主题演讲,他概述了需要一种低引脚数测试仪,具有较低性能的引脚电子器件,以满足10亿晶体管机器的严格测试成本要求。在2009年的ITC上,来自AMD的工程师提出了一种I/O测试解决方案,该解决方案使用现金自测试策略与外部低引脚数测试仪相结合,被认为可以满足英特尔的挑战。我们如何将主要挑战推向后硅验证和巨大变化时代?技术缩放使我们能够在振幅分辨率和时间分辨率之间进行权衡。因此,内部和外部测试(其中一些使用低引脚数测试仪)也从以电压为中心的测试转向以时间为中心的测试。如何使用时间分辨率来推动以时间为中心的测试超越当前的限制?如何实现空间分辨率以提高模间变化和模内变化的良率?什么是必要的,以提供强大的片上解决方案受制于巨大的变化,这可能与外部低引脚数测试仪相结合?
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