Pub Date : 2013-06-27DOI: 10.1109/VTS.2013.6548902
Bo Yao, Arani Sinha, I. Pomeranz
We describe a procedure based on an existing static timing analysis tool for selecting path delay faults to target during test generation. The use of an existing static timing analysis tool ensures that a state-of-the-art process can be used for estimating path delays. However, static timing analysis, by itself, can be inaccurate as it does not take into consideration conditions that are necessary for detecting path delay faults. In the proposed method, these conditions are captured as what are called input necessary assignments, which static timing analysis tools are able to use. By providing the static timing analysis process with the input necessary assignments for a selected path, the static timing analysis process can estimate the delay of the path more accurately. It can also identify additional paths whose delays are at least as high as those of the selected paths. Thus, feeding back the input necessary assignments to the static timing analysis process enhances the correlation between static timing analysis and actual timing of tests on silicon. The result is a set of potentially detectable path delay faults associated with critical paths based on more accurate estimates of the path delays that can be exhibited by a test set, compared with the set that would be obtained by static timing analysis alone.
{"title":"Path selection based on static timing analysis considering input necessary assignments","authors":"Bo Yao, Arani Sinha, I. Pomeranz","doi":"10.1109/VTS.2013.6548902","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548902","url":null,"abstract":"We describe a procedure based on an existing static timing analysis tool for selecting path delay faults to target during test generation. The use of an existing static timing analysis tool ensures that a state-of-the-art process can be used for estimating path delays. However, static timing analysis, by itself, can be inaccurate as it does not take into consideration conditions that are necessary for detecting path delay faults. In the proposed method, these conditions are captured as what are called input necessary assignments, which static timing analysis tools are able to use. By providing the static timing analysis process with the input necessary assignments for a selected path, the static timing analysis process can estimate the delay of the path more accurately. It can also identify additional paths whose delays are at least as high as those of the selected paths. Thus, feeding back the input necessary assignments to the static timing analysis process enhances the correlation between static timing analysis and actual timing of tests on silicon. The result is a set of potentially detectable path delay faults associated with critical paths based on more accurate estimates of the path delays that can be exhibited by a test set, compared with the set that would be obtained by static timing analysis alone.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130902930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548915
Kihyuk Han, Joon-Sung Yang, J. Abraham
As the complexity of integrated circuit design increases and production schedules become shorter, the dependency on post-silicon validation for capturing design errors that escape from pre-silicon verification also increases. A major challenge in post-silicon validation is the limited observability of internal states caused by the limited storage capacity available for post-silicon validation. Recent research has shown that observability can be enhanced if trace and scan signals are combined together, compared with the debugging scenario where only trace signals are monitored. This paper proposes an enhanced and systematic algorithm for the efficient combination of trace and scan signals to maximize the observability of internal circuit states. Experimental results on benchmark circuits show that the proposed technique provides a higher number of restored states compared to the existing techniques.
{"title":"Enhanced algorithm of combining trace and scan signals in post-silicon validation","authors":"Kihyuk Han, Joon-Sung Yang, J. Abraham","doi":"10.1109/VTS.2013.6548915","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548915","url":null,"abstract":"As the complexity of integrated circuit design increases and production schedules become shorter, the dependency on post-silicon validation for capturing design errors that escape from pre-silicon verification also increases. A major challenge in post-silicon validation is the limited observability of internal states caused by the limited storage capacity available for post-silicon validation. Recent research has shown that observability can be enhanced if trace and scan signals are combined together, compared with the debugging scenario where only trace signals are monitored. This paper proposes an enhanced and systematic algorithm for the efficient combination of trace and scan signals to maximize the observability of internal circuit states. Experimental results on benchmark circuits show that the proposed technique provides a higher number of restored states compared to the existing techniques.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125801690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548942
A. Chandra
A typical design today is implemented with DFT where the capture clocks are supplied on chip. The on-chip controller (OCC) plays a critical role in the application and the quality of the tests. Almost every design house has developed an innovative way of delivering either the structural tests or in house mix of structural-functional tests through the use of OCC and the design-for-test (DFT) implemented on the chip. Complexities in the implementation come due to the various test strategies employed with: • Process variation leading to issues like dealing with non-unique critical paths on every chip • Test data compression becoming primary DFT solution for manufacturing test • Low cost testers unable to keep up with the requirements of clocking schemes In this session, we want to explore the current offerings of the EDA tools to implement OCC based solutions and how the industry is going beyond those standard solutions to use innovative OCC based tests to provide a quality at-speed manufacturing test solution.
{"title":"Special session 11B: Hot topic on-chip clocking — Industrial trends","authors":"A. Chandra","doi":"10.1109/VTS.2013.6548942","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548942","url":null,"abstract":"A typical design today is implemented with DFT where the capture clocks are supplied on chip. The on-chip controller (OCC) plays a critical role in the application and the quality of the tests. Almost every design house has developed an innovative way of delivering either the structural tests or in house mix of structural-functional tests through the use of OCC and the design-for-test (DFT) implemented on the chip. Complexities in the implementation come due to the various test strategies employed with: • Process variation leading to issues like dealing with non-unique critical paths on every chip • Test data compression becoming primary DFT solution for manufacturing test • Low cost testers unable to keep up with the requirements of clocking schemes In this session, we want to explore the current offerings of the EDA tools to implement OCC based solutions and how the industry is going beyond those standard solutions to use innovative OCC based tests to provide a quality at-speed manufacturing test solution.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130106576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548904
R. Rashidzadeh
In this paper, three coupling techniques for contactless TSV probing have been presented and their advantages and disadvantages are discussed. A contactless, noninvasive TSV probing scheme based on the principle of capacitive coupling is designed and simulated. The implemented scheme supports the high-density and the tight-pitch requirements for TSV probing.
{"title":"Contactless test access mechanism for TSV based 3D ICs","authors":"R. Rashidzadeh","doi":"10.1109/VTS.2013.6548904","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548904","url":null,"abstract":"In this paper, three coupling techniques for contactless TSV probing have been presented and their advantages and disadvantages are discussed. A contactless, noninvasive TSV probing scheme based on the principle of capacitive coupling is designed and simulated. The implemented scheme supports the high-density and the tight-pitch requirements for TSV probing.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114092742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548928
P. Papavramidou, M. Nicolaidis
In modern SoCs embedded memories should be repaired to achieve acceptable yield. They should also be protected by ECC against field failures to achieve acceptable reliability. In technologies affected by high defect densities, conventional repair induce very high costs. To reduce them, we can use ECC to fix words comprising a single faulty cell and repair to fix all other faulty words. However it was shown that, for high defect densities, the diagnosis required for ECC-based repair may induce very large cost. In previous work this issue was fixed by means of new memory test algorithms that exhibit the so-called “single-read double-fault detection” property. As these algorithms are complex and increase test length, we explore a new iterative diagnosis approach, which provides tradeoffs in terms of hardware cost and test length.
{"title":"An iterative diagnosis approach for ECC-based memory repair","authors":"P. Papavramidou, M. Nicolaidis","doi":"10.1109/VTS.2013.6548928","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548928","url":null,"abstract":"In modern SoCs embedded memories should be repaired to achieve acceptable yield. They should also be protected by ECC against field failures to achieve acceptable reliability. In technologies affected by high defect densities, conventional repair induce very high costs. To reduce them, we can use ECC to fix words comprising a single faulty cell and repair to fix all other faulty words. However it was shown that, for high defect densities, the diagnosis required for ECC-based repair may induce very large cost. In previous work this issue was fixed by means of new memory test algorithms that exhibit the so-called “single-read double-fault detection” property. As these algorithms are complex and increase test length, we explore a new iterative diagnosis approach, which provides tradeoffs in terms of hardware cost and test length.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121516706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548898
A. Evans, M. Nicolaidis, R. Aitken, Burcin Aktan, Olivier Lauzeral
Today, there are several trends that are making the reliability analysis of complex integrated circuits an important challenge in industry. As transistor geometries shrink, the number of physical failure mechanisms is increasing while at the same time the number of transistors per chip is still growing. The rollout of new services is pushing compute demands both in handheld devices and in the data center which is driving up complexity and the level of integration. People are becoming critically dependent on mobile services and expect high availability. Looking forward to the deployment of the Internet of Things (IoT) where processors and routers will be embedded in billions of end-points, we are only going to see an increased demand for reliable computing. In this session, we bring together three different industrial perspectives on reliability. The first looks at the end-points, the second looks at the servers and the last looks at the economic drivers for reliability and the demand for new EDA tools for reliability analysis. In the first talk, Rob Aitken from ARM will discuss the reliability challenges in mobile applications. As mobile systems continue to increase in size and complexity, and user requirements are also becoming more stringent, it is important for designers of mobile systems to be aware of reliability issues, and to adapt their methodologies accordingly. This talk discusses the issues involved, from latent defects, through soft errors, aging and wearout, and shows how to consider these as part of the design process, how to quantify their effects, and how to mitigate them through design changes. In the second presentation, Burcin Aktan from Intel is going to discuss the evolution of the reliability features that are found in server applications. With so many processing units packed in data centers the reliability requirements on an individual device is growing, especially with integrated memory controllers and very high bandwidth data pathways. What was an “add-on” to a device function, 10–15 years ago, now needs to be considered carefully with stringent budgets distributed to each functional block that contribute to overall error rates. This talk will focus on the evolution of reliability features in a number of server products leading into the current state and look at how today's designers are dealing with the challenges of gathering requirements, translating these to design implementation and delivering quality features to customers. Finally we will close with remarks on future directions and possible research areas. In the final presentation, Olivier Lauzeral from iROC Technologies will discuss the importance of methodologies for the reliability analysis of complex SoCs. There is an inherent cost to adding reliability features in a complex IC and designers need to be able to make informed decisions about how much hardware to allocate for mitigation (redundancy, error correction, repair). A prerequisite to make such choices is
{"title":"Hot topic session 4A: Reliability analysis of complex digital systems","authors":"A. Evans, M. Nicolaidis, R. Aitken, Burcin Aktan, Olivier Lauzeral","doi":"10.1109/VTS.2013.6548898","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548898","url":null,"abstract":"Today, there are several trends that are making the reliability analysis of complex integrated circuits an important challenge in industry. As transistor geometries shrink, the number of physical failure mechanisms is increasing while at the same time the number of transistors per chip is still growing. The rollout of new services is pushing compute demands both in handheld devices and in the data center which is driving up complexity and the level of integration. People are becoming critically dependent on mobile services and expect high availability. Looking forward to the deployment of the Internet of Things (IoT) where processors and routers will be embedded in billions of end-points, we are only going to see an increased demand for reliable computing. In this session, we bring together three different industrial perspectives on reliability. The first looks at the end-points, the second looks at the servers and the last looks at the economic drivers for reliability and the demand for new EDA tools for reliability analysis. In the first talk, Rob Aitken from ARM will discuss the reliability challenges in mobile applications. As mobile systems continue to increase in size and complexity, and user requirements are also becoming more stringent, it is important for designers of mobile systems to be aware of reliability issues, and to adapt their methodologies accordingly. This talk discusses the issues involved, from latent defects, through soft errors, aging and wearout, and shows how to consider these as part of the design process, how to quantify their effects, and how to mitigate them through design changes. In the second presentation, Burcin Aktan from Intel is going to discuss the evolution of the reliability features that are found in server applications. With so many processing units packed in data centers the reliability requirements on an individual device is growing, especially with integrated memory controllers and very high bandwidth data pathways. What was an “add-on” to a device function, 10–15 years ago, now needs to be considered carefully with stringent budgets distributed to each functional block that contribute to overall error rates. This talk will focus on the evolution of reliability features in a number of server products leading into the current state and look at how today's designers are dealing with the challenges of gathering requirements, translating these to design implementation and delivering quality features to customers. Finally we will close with remarks on future directions and possible research areas. In the final presentation, Olivier Lauzeral from iROC Technologies will discuss the importance of methodologies for the reliability analysis of complex SoCs. There is an inherent cost to adding reliability features in a complex IC and designers need to be able to make informed decisions about how much hardware to allocate for mitigation (redundancy, error correction, repair). A prerequisite to make such choices is","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":" 14","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113950551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548885
H. Bossers, J. Hurink, G. Smit
Integrated circuits are tested thoroughly in order to meet the high demands on quality. As an additional step, outlier detection is used to detect potential unreliable chips such that quality can be improved further. However, it is often unclear to which tests outlier detection should be applied and how the parameters must be set, such that outliers are detected and yield loss remains limited. In this paper we introduce a mathematical framework, that given a set of target devices, can select tests for outlier detection and set the parameters for each outlier detection method. We provide results on real world data and analyze the resulting yield loss and missed targets.
{"title":"Selection of tests for outlier detection","authors":"H. Bossers, J. Hurink, G. Smit","doi":"10.1109/VTS.2013.6548885","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548885","url":null,"abstract":"Integrated circuits are tested thoroughly in order to meet the high demands on quality. As an additional step, outlier detection is used to detect potential unreliable chips such that quality can be improved further. However, it is often unclear to which tests outlier detection should be applied and how the parameters must be set, such that outliers are detected and yield loss remains limited. In this paper we introduce a mathematical framework, that given a set of target devices, can select tests for outlier detection and set the parameters for each outlier detection method. We provide results on real world data and analyze the resulting yield loss and missed targets.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133770196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548890
Koji Asami, T. Shimura, Toshiaki Kurihara
Since recent wireless communication devices support multiple communication standards on a single chip, Error Vector Magnitudes (EVMs) for multiple standards are measured to evaluate the devices. The EVM is defined by the particular calculation methods of the communication standards, especially channel correction methods. Therefore the EVM value is different between standards, even if the modulation methods are identical. This paper describes an EVM evaluation method for multi-standard devices, performing channel correction particular to each standard. The EVM for the various standards can be calculated by a unique algorithm, which uses the values of the frequency-dependent I/Q imbalances and the Signal-to-Noise Ratio (SNR) calculated from a single measurement data. The validity of this technique is confirmed using an actual WiMAX transceiver on an ATE.
{"title":"Novel estimation method of EVM with channel correction for linear impairments in multi-standard RF transceivers","authors":"Koji Asami, T. Shimura, Toshiaki Kurihara","doi":"10.1109/VTS.2013.6548890","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548890","url":null,"abstract":"Since recent wireless communication devices support multiple communication standards on a single chip, Error Vector Magnitudes (EVMs) for multiple standards are measured to evaluate the devices. The EVM is defined by the particular calculation methods of the communication standards, especially channel correction methods. Therefore the EVM value is different between standards, even if the modulation methods are identical. This paper describes an EVM evaluation method for multi-standard devices, performing channel correction particular to each standard. The EVM for the various standards can be calculated by a unique algorithm, which uses the values of the frequency-dependent I/Q imbalances and the Signal-to-Noise Ratio (SNR) calculated from a single measurement data. The validity of this technique is confirmed using an actual WiMAX transceiver on an ATE.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115102917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548905
Chun-Chuan Chi, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin
Through-Silicon-Via (TSV)-based three-dimensional ICs (3D-ICs) have gained increasing attention due to their potential in reducing manufacturing costs and capability of integrating more functionality into a single chip. One of the most important factors that affect 3D-IC yield is the integrity of interconnects which connect different dies in a 3D-IC. This paper proposes a Design-for-Test (DIT) scheme that can 1) detect faulty interconnects in 3D-ICs, 2) pinpoint open defect locations to help yield learning, and 3) repair faulty interconnects caused by open defects to improve the 3D-IC yield. Experimental results show that the proposed scheme can achieve a diagnosis resolution of 84% for open defects. With the interconnect repair mechanism, the 3D-IC yield is improved by 10%. In addition, cost-benefit analysis reveals that the proposed technique can significantly increase the net profit, especially when the natural interconnect yield is low.
{"title":"3D-IC interconnect test, diagnosis, and repair","authors":"Chun-Chuan Chi, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin","doi":"10.1109/VTS.2013.6548905","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548905","url":null,"abstract":"Through-Silicon-Via (TSV)-based three-dimensional ICs (3D-ICs) have gained increasing attention due to their potential in reducing manufacturing costs and capability of integrating more functionality into a single chip. One of the most important factors that affect 3D-IC yield is the integrity of interconnects which connect different dies in a 3D-IC. This paper proposes a Design-for-Test (DIT) scheme that can 1) detect faulty interconnects in 3D-ICs, 2) pinpoint open defect locations to help yield learning, and 3) repair faulty interconnects caused by open defects to improve the 3D-IC yield. Experimental results show that the proposed scheme can achieve a diagnosis resolution of 84% for open defects. With the interconnect repair mechanism, the 3D-IC yield is improved by 10%. In addition, cost-benefit analysis reveals that the proposed technique can significantly increase the net profit, especially when the natural interconnect yield is low.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125798742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548946
A. Sanyal, Y. Zorian
IEEE Test Technology Technical Council (TTTC) takes an initiative to establish a forum involving young professionals working in the broad domain of test, diagnosis, yield improvement and related areas. We have formed a panel involving a diversified group of young professionals (recent PhD graduates from US and Canadian universities) currently employed in the leading US semiconductor and EDA companies. The session will be held in town-hall format, organized by Dr. Alodeep Sanyal from Synopsys and Dr. Yanjing Lin from Intel, and moderated by Dr. Yervant Zorian from Synopsys. The panelists will be involved in discussing the objectives of this newly-formed TTTC forum and the activities it should monitor. Some of the topics of discussion may include: (a) The benefits that TTTC can offer to the young professionals; (b) Establishing a connection between working professionals and graduate students that may provide research/mentoring opportunities for the professionals; (c) An actively maintained job requisition database exclusively available under TTTC for the student members to help them apply for a suitable job. The overall topic of discussion for this panel has been left quite open-ended for participants to propose their own ideas. We expect this panel will identify the future direction and activities for the TTTC Young Professionals Forum.
{"title":"Special session 12C: Town-hall meeting “young professionals in test”","authors":"A. Sanyal, Y. Zorian","doi":"10.1109/VTS.2013.6548946","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548946","url":null,"abstract":"IEEE Test Technology Technical Council (TTTC) takes an initiative to establish a forum involving young professionals working in the broad domain of test, diagnosis, yield improvement and related areas. We have formed a panel involving a diversified group of young professionals (recent PhD graduates from US and Canadian universities) currently employed in the leading US semiconductor and EDA companies. The session will be held in town-hall format, organized by Dr. Alodeep Sanyal from Synopsys and Dr. Yanjing Lin from Intel, and moderated by Dr. Yervant Zorian from Synopsys. The panelists will be involved in discussing the objectives of this newly-formed TTTC forum and the activities it should monitor. Some of the topics of discussion may include: (a) The benefits that TTTC can offer to the young professionals; (b) Establishing a connection between working professionals and graduate students that may provide research/mentoring opportunities for the professionals; (c) An actively maintained job requisition database exclusively available under TTTC for the student members to help them apply for a suitable job. The overall topic of discussion for this panel has been left quite open-ended for participants to propose their own ideas. We expect this panel will identify the future direction and activities for the TTTC Young Professionals Forum.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129732984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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