Validation of on-wafer vector network analyzer systems

Abstract

The case study described in this paper applies a known vector network analyzer comparison technique to an on-wafer measurement environment. The purpose is to investigate and expand upon this technique's applicability for use in validating an on-wafer VNA system of unknown accuracy by comparing it to an on-wafer VNA system of trusted accuracy. The technique involves taking calibrated S-Parameter measurements with each system over a set of validation devices and calculating the measurement differences between the two systems. These differences are then compared to the estimated repeatability uncertainty bounds of the two VNAs in order to validate or invalidate the unknown system's capabilities. Results and limitations of this procedure are discussed.