Electro-chemical deposition technology for ULSI multilevel copper interconnects

C. Ting, D. Papapanayiotou, Mei Zhu
{"title":"Electro-chemical deposition technology for ULSI multilevel copper interconnects","authors":"C. Ting, D. Papapanayiotou, Mei Zhu","doi":"10.1109/ICSICT.1998.785852","DOIUrl":null,"url":null,"abstract":"Copper is a promising candidate to replace aluminum for better conductivity, reliability as well as lower cost. A new electrochemical copper deposition (ECD) process has been developed for the manufacturing of ULSI damascened, or in-laid, Cu interconnects. The new Cu ECD process-is designed for filling trenches and vias with high aspect ratio (AR) conductor structures for 0.25 um device generation and beyond. The gap filling Cu deposition process is capable of high deposition rate and gives good material properties as well as good uniformity. The newly developed Cu ECD system has a standard cluster tool configuration. Its deposition modules have in-situ rinse/dry capability to achieve cassette to cassette dry wafer in and dry wafer out operations. Dual damascene structures with 0.4 um feature size and AR 5:1, which represents the most aggressive device structure being made today, have been completely filled without voids or seams. In addition, deep contact test structures with 0.25 um feature size and AR 8:1 have also been filled to demonstrate the capabilities of this new technology.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.1998.785852","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

Copper is a promising candidate to replace aluminum for better conductivity, reliability as well as lower cost. A new electrochemical copper deposition (ECD) process has been developed for the manufacturing of ULSI damascened, or in-laid, Cu interconnects. The new Cu ECD process-is designed for filling trenches and vias with high aspect ratio (AR) conductor structures for 0.25 um device generation and beyond. The gap filling Cu deposition process is capable of high deposition rate and gives good material properties as well as good uniformity. The newly developed Cu ECD system has a standard cluster tool configuration. Its deposition modules have in-situ rinse/dry capability to achieve cassette to cassette dry wafer in and dry wafer out operations. Dual damascene structures with 0.4 um feature size and AR 5:1, which represents the most aggressive device structure being made today, have been completely filled without voids or seams. In addition, deep contact test structures with 0.25 um feature size and AR 8:1 have also been filled to demonstrate the capabilities of this new technology.
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ULSI多层铜互连的电化学沉积技术
铜具有更好的导电性、可靠性和更低的成本,是替代铝的一个有希望的候选者。开发了一种新的电化学铜沉积(ECD)工艺,用于制造ULSI衬垫或嵌套铜互连。新的Cu ECD工艺专为填充具有高纵横比(AR)导体结构的沟槽和过孔而设计,适用于0.25 um及以上的器件生产。该工艺具有沉积速率高、材料性能好、均匀性好的优点。新开发的Cu ECD系统具有标准的群集工具配置。其沉积模块具有原位冲洗/干燥能力,可实现盒式到盒式干晶圆片输入和干晶圆片输出操作。具有0.4 um特征尺寸和5:1的双大马士革结构,代表了当今最具侵略性的设备结构,已经完全填充,没有空隙或接缝。此外,还填充了0.25 um特征尺寸和AR 8:1的深度接触测试结构,以展示这项新技术的能力。
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