An analysis of the effect of wire resistance on circuit level performance at the 45-nm technology node

V. H. Nguyen, P. Christie, A. Heringa, A. Kumar, R. Ng
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引用次数: 9

Abstract

The paper presents a method for assessing the impact of interconnects on dynamic system level performance. The method is applied to the analysis of the impact of interconnect parasitic resistance and capacitance on the performance of different circuit types at the 45-nm technology node. It is observed that the interconnect capacitance dominates circuit performance at short interconnect lengths. The interconnect resistance influences low-power (high-speed) circuit speed only for critical wire lengths longer than 360 /spl mu/m (180 /spl mu/m). Within the investigated interconnect lengths, the interconnect resistance has virtually no impact on the switching energy of the test circuit. The results indicate that for low-power circuits, the high interconnect resistance is not a serious issue at the 45-nm technology node.
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在45nm技术节点上导线电阻对电路级性能的影响分析
本文提出了一种评估互连对动态系统级性能影响的方法。应用该方法分析了在45nm工艺节点上,互连寄生电阻和电容对不同电路类型性能的影响。在较短的互连长度下,互连电容决定了电路的性能。只有当临界导线长度大于360 /spl mu/m (180 /spl mu/m)时,互连电阻才会影响低功率(高速)电路速度。在所研究的互连长度范围内,互连电阻对测试电路的开关能量几乎没有影响。结果表明,对于低功耗电路,在45纳米技术节点上,高互连电阻不是一个严重的问题。
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