The design of stable logic input inversion level on IC chip

Abstract

In whole system, the user usually only offers a voltage with noise as input logic voltage to digital receiver, to guarantee the right logic control, it requires that the IC chip must have a stable inversion level with logic high and logic low input voltage. For COMS process, in traditional design scheme, it usually uses a normal digital inverter as input-unit schematic, and changes the width or length in PMOS and NMOS to change the inversion level of digital receiver. But in this way, the inversion level is depends on process, and it also will be changed with temperature or power noise, for whole system, it is very bad. So this paper introduces three kinds of stable inversion level schematic. They all use the degenerative feedback to stable inversion level. It completely depends on schematic of input-port in receiver, and is also very stable with temperature and power noise.