Noise analysis and optimization of a unity gain sampler

Abstract

Noise analysis of a widely used switched capacitor unity gain sampler is presented, which in detail shows that the circuit structure can not only get rid of the offset voltage induced by the OTA involved, but also has the ability of suppressing 1/f noise with operation timing of the sampling capacitor, functioning as correlated double sampling in fact, however paying the price of increasing thermal noise. The noise analysis method starts from establishing noise model for the sampler in each individual clock phase. Then based on the characteristic of charge transferring by capacitors and theory of random process, the output noise power contributed by each noise source is derived, the key point of which is that how to determine whether the process of some noise source in some phase transferring to the output node is effected by filtering. At last optimization design for the capacitor elements, which determine the whole noise power, is conducted.