{"title":"A 2-Channel ADC Using a Delta-Sigma Modulator Without Reset & a Modulated-Sinc-Sum Filter","authors":"R. S. A. Kumar, N. Krishnapura","doi":"10.1109/ESSCIRC.2019.8902610","DOIUrl":null,"url":null,"abstract":"A new method is proposed for converting any continuously running discrete-time delta-sigma modulator to a multi-channel ADC by modifying only the digital filters. The two input channels are multiplexed and fed to the modulator. The cross-talk that would exist, if the output of the decimation filter is demultiplexed directly, is canceled using a modulated-sinc-sum digital filter, operating at the downsampled rate. This technique avoids reset that is required in incremental ADCs and the input sample-and-hold that is required in previously proposed techniques for multi-channel conversion without reset. A prototype two-channel ADC clocked at 6.144 MHz with a per-channel bandwidth of 22 kHz is demonstrated in a 180 nm CMOS process. It consumes 1.53 mW/channel including the digital filters and achieves a peak SNR/DR of 94.4 dB/98.5 dB, while restricting the inter-channel cross-talk to less than −94 dBc.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2019.8902610","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A new method is proposed for converting any continuously running discrete-time delta-sigma modulator to a multi-channel ADC by modifying only the digital filters. The two input channels are multiplexed and fed to the modulator. The cross-talk that would exist, if the output of the decimation filter is demultiplexed directly, is canceled using a modulated-sinc-sum digital filter, operating at the downsampled rate. This technique avoids reset that is required in incremental ADCs and the input sample-and-hold that is required in previously proposed techniques for multi-channel conversion without reset. A prototype two-channel ADC clocked at 6.144 MHz with a per-channel bandwidth of 22 kHz is demonstrated in a 180 nm CMOS process. It consumes 1.53 mW/channel including the digital filters and achieves a peak SNR/DR of 94.4 dB/98.5 dB, while restricting the inter-channel cross-talk to less than −94 dBc.