GeneSys: a leaf-cell layout synthesis system for GHz VLSI designs

Abstract

We present a new VLSI layout tool that synthesizes leaf-cell layouts for custom designs as well as standard cell and datapath libraries. GeneSys takes a leaf-cell schematic and a variety of top-down constraints to produce a layout for the circuit. The tool consists of five main components: placer, router, compactor, reliability analyzer and family generator. The system features new 2-D device placement and routing algorithms driven by reliability constraints. A Cell Architecture Rules feature allows customization of the tool to various layout styles. The family generation feature allows rapid synthesis of layout families from template cells. Initial usage statistics show a 2-4X mask designer productivity improvement for a variety of cells.