Effective Post-BIST Fault Diagnosis for Multiple Faults

Abstract

With the increasing complexity of LSI, built-in self test (BIST) is one of the promising techniques in the production test. From our observation during the manufacturing test, multiple stuck-at faults often exist in the failed chips during the yield ramp-up. Therefore the authors propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. The fault diagnosis based on the compressed responses from BIST was called the post-BIST fault diagnosis (Takahashi et al., 2005, Takamatsu, 2005). The efficiency on the success ratio and the feasibility of diagnosing large circuits are discussed. From the experimental results for ISCAS and STARC03 (Sato et al., 2005) benchmark circuits, it is clear that high success ratios that are about 98% are obtained by the proposed diagnosis method. From the experimental result for the large circuits with 100K gates, the feasibility of diagnosing the large circuits within the practical CPU times can be confirmed. The feasibility of diagnosing multiple stuck-at faults on the post-BIST fault diagnosis was proven