{"title":"A 94 GHz programmable frequency divider with inductive peaking for wideband and highly stable frequency synthesizers","authors":"M. van Delden, N. Pohl, K. Aufinger, T. Musch","doi":"10.23919/EUMIC.2017.8230647","DOIUrl":null,"url":null,"abstract":"We present a fully programmable frequency divider in two different versions operating at input frequencies from DC to 94 GHz and 92 GHz, respectively, for the use in wideband and highly stable millimeter-wave frequency synthesizers. Using a parallel interface the division factors can be programmed to all integer values between 12 and 259. The high input speed in conjunction with programmability is achieved by a dual-modulus concept utilizing gates in emitter-coupled logic with inductive shunt peaking and by merging logic functions into flip-flops. The two versions utilize different differential spiral inductors. The frequency dividers were realized in a SiGe BiCMOS technology with fT = 250 GHz and are draining a current of 120 mA from a 3.3 V supply.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/EUMIC.2017.8230647","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
We present a fully programmable frequency divider in two different versions operating at input frequencies from DC to 94 GHz and 92 GHz, respectively, for the use in wideband and highly stable millimeter-wave frequency synthesizers. Using a parallel interface the division factors can be programmed to all integer values between 12 and 259. The high input speed in conjunction with programmability is achieved by a dual-modulus concept utilizing gates in emitter-coupled logic with inductive shunt peaking and by merging logic functions into flip-flops. The two versions utilize different differential spiral inductors. The frequency dividers were realized in a SiGe BiCMOS technology with fT = 250 GHz and are draining a current of 120 mA from a 3.3 V supply.