A High-Speed Optical Receiver Front-end for Single Photon Avalanche Diodes (SPADs)

Abstract

A single-ended negative capacitor (SNC) circuit in CMOS technology is presented in this paper. Using this circuit, the effect of parasitic capacitances and quenching time (TQ) of single photon avalanche diodes (SPADs) can be reduced. To demonstrate efficiency of the proposed technique, two different quenching circuits are designed and simulated. In these simulations, a behavioral model in VerilogA is introduced. Simulation results show that the quenching time is reduced by 38% and 74% in the circuits by employing the proposed SNC topology.