Design of energy efficient 10ps per bit adder circuits in CMOS

Abstract

This work presents the experimental results, from chip measurements, of ripple carry adder circuits using a new CMOS logic family-feedthrough logic (FTL). A 14-bit low power FTL adder performs faster, (2.6 times smaller propagation time delay, and 1.85 times higher maximum frequency), and provides a better energy efficiency (67.9% saving), when compared with the dynamic domino CMOS logic style. The 18-bit high speed FTL, working at its maximum frequency, outperforms the dynamic domino logic in terms of the propagation delay (19.5 times less), maximum frequency (12.1 times more), and energy efficiency per bit (96.7% better).