A 3.8 ns CMOS 16×16 multiplier using complementary pass transistor logic

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56843

K. Yano, T. Yamanaka, T. Nishida, M. Saitoh, K. Shimohigashi, A. Shimizu

引用次数: 65

Abstract

A 3.8-ns, 257-mW CMOS 16×16 multiplier with a supply voltage of 4 V is described. A complementary pass transistor logic (CPL) is proposed and applied to almost the entire critical path. The CPL consists of complementary input/output, an NMOS-pass-transistor logic network, and CMOS output inverters. The CPL is twice as fast as the conventional CMOS due to lower input capacitance and greater logic construction ability. Its multiplication time is believed to be the fastest ever reported, even including times of bipolar and GaAs ICs, and it is shown to be further enhanced to 2.6 ns and 60 mW at 77 K

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采用互补通型晶体管逻辑的3.8 ns CMOS 16倍乘法器

描述了一种3.8 ns、257 mw、电源电压为4 V的CMOS 16×16乘法器。提出了一种互补通型晶体管逻辑(CPL)，并应用于几乎整个关键路径。CPL由互补输入/输出、CMOS通管逻辑网络和CMOS输出逆变器组成。由于更低的输入电容和更强的逻辑构造能力，CPL的速度是传统CMOS的两倍。它的倍增时间被认为是有史以来最快的，甚至包括双极和GaAs ic的倍增时间，并且在77 K下进一步提高到2.6 ns和60 mW

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1989 Proceedings of the IEEE Custom Integrated Circuits Conference

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