Design and implementation of a Viterbi decoder using FPGAs

Abstract

This paper describes the design at implementation of Viterbi decoder using FPGAs. In this paper we explore an FPGA based implementation methodology for rapidly prototyping designs. We use high level synthesis to achieve this. Some of the implementation issues related to the Viterbi decoder such as organization of path memory, decision memory reading techniques, and the clocking mechanism have been discussed.