{"title":"63.2pS at 1.2V dynamic comparator in 65nm CMOS technology","authors":"Jun Yuan, Xiaobin Tang","doi":"10.1109/ISOCC47750.2019.9027693","DOIUrl":null,"url":null,"abstract":"A high speed dynamic comparator is proposed. The speed of the comparator is improved by reducing the voltage of the shared nodes of the input stage and latch stage. The proposed dynamic comparator has been designed and simulated using 65nm CMOS technology. The simulation results show that the proposed comparator achieved 63.2ps delay at 1.2V power supply","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC47750.2019.9027693","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A high speed dynamic comparator is proposed. The speed of the comparator is improved by reducing the voltage of the shared nodes of the input stage and latch stage. The proposed dynamic comparator has been designed and simulated using 65nm CMOS technology. The simulation results show that the proposed comparator achieved 63.2ps delay at 1.2V power supply
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