Layout optimizations for THz integrated circuit design in bulk nanometer CMOS

Abstract

Scaling in CMOS has increased the attainable operational frequencies, while greatly increasing the transistor's parasitic modeling complexity. Additionally, the performance of the ever-smaller on-chip passives for mm-wave and THz circuits is being degraded by numerous process requirements and limitations, such as high densities of dummy metals. This work discusses the main transistor layout trade-offs for high-frequency performance in both 40nm and 28nm bulk CMOS. The impact of dummy metals on a single-turn on-chip inductor for mm-wave/THz frequencies is presented, which shows that low dummy metal densities around critical high-frequency passives are essential to minimize degradation in performance.