Characterization of peripheral and core SSOs in a flip-chip package

R. Kollipara, L. Lin, G. Oehrle
{"title":"Characterization of peripheral and core SSOs in a flip-chip package","authors":"R. Kollipara, L. Lin, G. Oehrle","doi":"10.1109/EPEP.1997.634053","DOIUrl":null,"url":null,"abstract":"Electrical characterization of various SSO (simultaneous switching output) buffers placed on the periphery and in the core of a flip-chip is performed. The multilayer CBGA package has multiple power and ground planes and signal routing layers. Methodology guide lines are developed based on the characterization results.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"108 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Performance of Electronic Packaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.1997.634053","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

Electrical characterization of various SSO (simultaneous switching output) buffers placed on the periphery and in the core of a flip-chip is performed. The multilayer CBGA package has multiple power and ground planes and signal routing layers. Methodology guide lines are developed based on the characterization results.
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倒装封装中外设和核心sso的特性
对放置在倒装芯片外围和核心的各种SSO(同步开关输出)缓冲器进行了电气特性分析。多层CBGA封装具有多个电源层、接地层和信号路由层。方法学指导方针是根据表征结果制定的。
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