Thermal analysis of ultra-thin body device scaling [SOI and FinFet devices]

Abstract

This paper explores the effect of confined dimensions and complicated geometries on the self-heating of ultra-thin body SOI and FinFET devices. A compact thermal model is introduced, incorporating the most advanced understanding of nanoscale heat conduction available. Novel device scaling is analyzed from a thermal point of view. We show device temperatures are very sensitive to the choice of drain and channel extension dimensions, and suggest a parameter design space which can help alleviate thermal problems. ITRS power guidelines below the 25 nm technology node should be revised if isothermal scaling of thin-body devices is desired.