State-of-Art Analysis of Multiplier designs for Image processing and Convolutional Neural Network Applications

Abstract

Recently, due to the immense growth of computing power, image processing and Convolutional neural networks (CNN) have regained gigantic attention because of the exemplary performance in Image modification and classification applications. The multipliers are the indispensable circuit components in improving energy efficiency of hardware implementations of CNN and image processing techniques. In this paper, we have presented a comprehensive study on state-of-the-art multipliers for these applications. Hardware platforms for deploying image processing and CNN are briefly described and multiplier implementation on these are discussed. A detailed discussion on FPGA based embedded multipliers and ASIC based multipliers is presented. Emerging multiplier architectures for CNN applications are compared. The strategies used for designing approximate multipliers and error compensation are also summarized.