Transistor reordering rules for power reduction in CMOS gates

W. Shen, Jiing-Yuan Lin, F. Wang
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引用次数: 27

Abstract

The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power consumption. In this paper, based on the input signal probabilities and transition densities, we propose a set of simple transistor reordering rules for both basic and complex CMOS gates to minimize the transition counts at the internal nodes. The most attractive feature of this approach is that not only the power consumption is reduced efficiently, but also the other performances are not degraded. Experimental results show that this technique typically reduces the power by about 10% in average, but in some cases the improvement is even 35%.
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降低CMOS栅极功率的晶体管重排序规则
逻辑门晶体管重排序的目标是减少传输延迟以及内部电容的充放电,以实现低功耗。在本文中,我们基于输入信号概率和跃迁密度,提出了一套简单的晶体管重排规则,用于基本和复杂的CMOS门,以最小化内部节点的跃迁计数。这种方法最吸引人的特点是不仅有效地降低了功耗,而且其他性能也没有下降。实验结果表明,该技术通常平均降低约10%的功率,但在某些情况下甚至可以提高35%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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