VLSI Implementation of a Fault-Tolerant Distributed Clock Generation

Abstract

In this paper the authors introduce a novel approach for the on-chip generation of a fault-tolerant clock. The authors motivate why it becomes more and more desirable to provide VLSI circuits with fault-tolerant clocking methods and how this fault tolerance can be achieved. The proposed clock generation method is based on the adaptation of a well known distributed clock synchronization algorithm which has been adapted for hardware implementation. The authors present the underlying algorithm, point out the difficulties for the hardware implementation and provide a detailed description of the resulting VLSI implementation. To emphasize the feasibility of the proposed fault-tolerant clock generation method the authors also present some measurement results from a prototype implementation