A 177 K gate 150 PS CMOS SOG with 1856 I/O buffers

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56715

M. Murayama, Y. Matsuda, K. Yoshida, H. Ooka, T. Otani, S. Toyoda, F. Tsubokura, A. Aso

引用次数: 2

Abstract

A CMOS SOG (sea-of-gates) that contains 177 K raw gates, corresponding to 1.4 M transistors and having a delay time of as fast as 150 ps, has been developed in a 0.8-μm CMOS technology. The SOG can accommodate a RAM of either a high-density type with 64 K bits maximum, a high-speed type with 6-ns access time, or a mixture of both. The SOG contains 1856 I/O buffers in the peripheral area of the die, providing high flexibility for interfacing circuits to the SOG

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

一个177k门150ps CMOS SOG与1856 I/O缓冲器

采用0.8 μ M的CMOS技术，开发出了包含177 K原始门、对应1.4 M晶体管、延迟时间快至150 ps的CMOS SOG (sea-of-gates)。SOG可以容纳最大64k位的高密度型RAM，访问时间为6ns的高速型RAM，或者两者的混合。SOG包含1856个I/O缓冲区，位于芯片外围区域，为SOG的接口电路提供了高度的灵活性

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊

1989 Proceedings of the IEEE Custom Integrated Circuits Conference

自引率

0.00%

发文量

期刊最新文献

A 1.4 ns/64 kb RAM with 85 ps/3680 logic gate array A gate matrix deformation and three-dimensional maze routing for dense MOS module generation A submicron CMOS triple level metal technology for ASIC applications Hot carrier effects on CMOS circuit performance The QML-an approach for qualifying ASICs