{"title":"An 11 GHz–Bandwidth Variable Gain Ka–Band Power Amplifier for 5G Applications","authors":"R. Bagger, H. Sjöland","doi":"10.1109/ESSCIRC.2019.8902927","DOIUrl":null,"url":null,"abstract":"A Ka–band, 32–43 GHz, differential power amplifier (PA) for millimeter wave applications is presented. The PA is a three stage design with a nominal gain of 36 dB. A device periphery ratio of 1:2:4 is adopted for pre–driver, driver and final stage, respectively. To enable use of 2.7 V supply, a cascode topology was employed in all three stages. The input is 80 Ω differential and the output load is 50 Ω single ended. The PA has a variable gain of 36 ± 11 dB for use as variable gain amplifier. A saturation power of 17.8 dBm was measured at 35 GHz with a small signal gain of 34.5 dB, including output losses of 2–2.5 dB over band. The design is based on magnetically coupled parallel resonators to obtain the required bandwidth. A SiGe HBT BiCMOS process with fMAX = 330 GHz was used for fabrication. The PA is part of a front–end design, and its output thus faces an antenna interface with integrated LNA and TX/RX switches, and the input is connected to an on-chip variable gain amplifier.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2019.8902927","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A Ka–band, 32–43 GHz, differential power amplifier (PA) for millimeter wave applications is presented. The PA is a three stage design with a nominal gain of 36 dB. A device periphery ratio of 1:2:4 is adopted for pre–driver, driver and final stage, respectively. To enable use of 2.7 V supply, a cascode topology was employed in all three stages. The input is 80 Ω differential and the output load is 50 Ω single ended. The PA has a variable gain of 36 ± 11 dB for use as variable gain amplifier. A saturation power of 17.8 dBm was measured at 35 GHz with a small signal gain of 34.5 dB, including output losses of 2–2.5 dB over band. The design is based on magnetically coupled parallel resonators to obtain the required bandwidth. A SiGe HBT BiCMOS process with fMAX = 330 GHz was used for fabrication. The PA is part of a front–end design, and its output thus faces an antenna interface with integrated LNA and TX/RX switches, and the input is connected to an on-chip variable gain amplifier.