Potential of thin (∼10 nm) HfO2 ferroelectric FDSOI NCFET for performance enhancement in digital circuits at reduced power consumption

Abstract

A simulation study using thin (∼10 nm) HfO2 PGP FDSOI NCFET based gates is presented. The study has been performed on devices having 20 nm metal gate length with supply voltage varying from 0.5 V to 0.9 V. The circuits studied were 3-stage ring oscillator, NAND-2 and NOR-2 gates. The study showed significant enhancement in the performance in HfO2 FDSOI NCFET based gates at reduced power consumption which is −66% when compared to that of FDSOI MOSFET based gates. The power-delay product of HfO2 FDSOI NCFET based gates was found to be significantly lower (∼24%) in comparison to baseline FDSOI MOSFET based gates. The effect of increasing fan-in and fan-out on the performance of logic gates has also been discussed in the paper.