Spintronics primitive gate with high error correction efficiency 6(Perror)2 for logic-in memory architecture

Abstract

A spintronics primitive gate with redundancy was designed using domain wall motion (DWM) cells, and the data-missing rate was drastically improved to ~6 (Perror)2 when the error rate per DWM cell was Perror. All the DWM cells aligned in series were written simultaneously, which suppressed the increase in power consumption when writing. Application of 4-terminal DWM cells with physically separated current paths for writing and reading saved extra path transistors for redundancy and there were no area overheads.