M. Khafaji, Jan Plíva, M. Zoldak, R. Henker, F. Ellinger
{"title":"A 42 Gbps VCSEL driver with adjustable 2-tap feed-forward equalizer in 14 nm SOI CMOS","authors":"M. Khafaji, Jan Plíva, M. Zoldak, R. Henker, F. Ellinger","doi":"10.23919/EUMIC.2017.8230689","DOIUrl":null,"url":null,"abstract":"In this paper the design and measurement results of a 42 Gbps vertical-cavity surface-emitting laser (VCSEL) driver is presented. A 2-tap feed-forward equalizer (FFE) architecture with adjustable delay is chosen and optimized to decrease the inter-symbol interference of the VCSEL data transmission. Circuit realizations of different blocks are presented as well. The chip was fabricated in a 14 nm SOI CMOS technology and bonded to a common-cathode 20 GHz VCSEL. Optical measurements show that error-free data transmission up to a data rate of 42 Gbps was possible. The total power dissipation, including the one of the VCSEL, is 117 mW, which provides a power efficiency of 2.8 pJ/bit. To the best of the author's knowledge, this is fastest VCSEL driver circuit in a CMOS technology presented so far.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/EUMIC.2017.8230689","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
In this paper the design and measurement results of a 42 Gbps vertical-cavity surface-emitting laser (VCSEL) driver is presented. A 2-tap feed-forward equalizer (FFE) architecture with adjustable delay is chosen and optimized to decrease the inter-symbol interference of the VCSEL data transmission. Circuit realizations of different blocks are presented as well. The chip was fabricated in a 14 nm SOI CMOS technology and bonded to a common-cathode 20 GHz VCSEL. Optical measurements show that error-free data transmission up to a data rate of 42 Gbps was possible. The total power dissipation, including the one of the VCSEL, is 117 mW, which provides a power efficiency of 2.8 pJ/bit. To the best of the author's knowledge, this is fastest VCSEL driver circuit in a CMOS technology presented so far.