Test width compression for built-in self testing

Abstract

We present a method for designing test generator circuits (TGCs) that incorporate a precomputed test set to in the patterns they produce. Our method uses width compression based on the property of d-compatibles, which allows us to encode to more efficiently than previous methods that use only compatibles and inverse compatibles. The TGC consists of a counter, which generates a set of encoded test patterns, and a decompression circuit consisting of simple binary decoders that generate a final sequence containing T/sub D/. These TGCs are applicable to embedded-core circuits whose detailed designs are not available. We demonstrate the effectiveness of our approach by presenting experimental results for the ISCAS 85 and ISCAS CAS 89 benchmark circuits.