10.3-Gb/s burst-mode CDR with idle insertion and digital calibration in 40-nm CMOS for 10G-EPON systems

Abstract

A burst-mode CDR (B-CDR) suffers from a trade-off between jitter transfer and lock time. To solve the trade-off, we utilize a continuous-mode CDR (C-CDR) after a B-CDR with converting the burst signal to the quasi-continuous signal by idle insertion. The B-CDR, designed in 40-nm CMOS, also employs a fully digital, 6-bit automatic frequency calibrator for compensating the process variation. It calibrates the oscillation frequency of the VCO in the B-CDR from 10.3 GHz ± 2 GHz to 10.3 GHz ± 60 MHz. The B-CDR, integrated with the C-CDR, achieves output-data-jitter reduction of 17.3 dB at jitter frequency of 300 MHz and lock time of 220 ns, complying with the 10G-EPON standard.