S. Morvan, F. Andrieu, P. Nguyen, J. Hartmann, M. Cassé, C. Tabone, A. Toffoli, F. Allain, W. Schwarzenbach, G. Ghibaudo, B. Nguyen, N. Daval, M. Haond, T. Poiroux, O. Faynot
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引用次数: 0
Abstract
We fabricated highly stressed FDSOI pMOSFETs down to 15nm gate length. The impact of different stressors (CESL, raised sources and drains, STI) is studied for different device geometries and channel orientations (<;100>; or <;110>;). We evidence that pMOSFETs along <;110>; are more sensitive to stress: STI degrades narrow devices compared to wide ones whereas compressive CESL (-3GPa) and SiGe S/D improve performances (+133% mobility, +16% ION on 10μm wide devices). This makes the <;110>; orientation the most favorable channel orientation for strained pMOSFETs on planar FDSOI.
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