Mixed-level defect simulation in data-paths of digital systems

Abstract

A new method for mixed level fault simulation of Data-Paths in Digital Systems represented with Decision Diagrams (DD) is proposed. We suppose that a register transfer level (RTL) information along with gate-level descriptions for RTL blocks are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits on both levels. The physical defects in the system are mapped to the logic level and are simulated on the mixed gateand RT levels. The approach proposed allows to increase the accuracy of test quality estimation, and to reduce simulation cost in comparison to traditional gate-level fault simulation methods.