A 8.4Gb/s Low Power Transmitter with 1.66 pJ/b using 40:1 Serializer for DisplayPort Interface

Abstract

This paper presents the design of the 8.4Gb/s transmitter with a two-tap feed-forward equalizer (FFE) and a 40:1 serializer. The transmitter includes an all-digital phased-locked-loop (ADPLL), a pre-driver and a driver. The simple architecture of the 5:1 serializer achieves low-power consumption by eliminating delay line buffers used to secure timing margin and the selection generator in the conventional 5:1 serializers. The prototype is fabricated in a 40-nm CMOS technology. It offers 72.5-ps eye width, which is 61% of the unit interval and exhibits energy efficiency of 1.66 pJ/bit at 8.4Gb/s.