Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates

Abstract

This paper presents simulations of 3 different implementations of the minority-3 function, with special focus on mismatch analysis through statistical Monte Carlo simulations. The simulations clearly favors the minority-3 mirrored gate, and a gate-level redundancy scheme, where identical circuits with the same input drive the same output-node, is further explored as a means of increasing fault- and defect-tolerance. Important tradeoffs between supply voltage, redundancy and yield are revealed, and VDD = 175 mV is suggested as a minimum useful operating voltage, combined with a redundancy factor of 2