A low-noise low-offset CMOS readout circuit for MEMS capacitive accelerometers

Abstract

This paper describes a low-noise low-offset CMOS readout circuit for MEMS capacitive accelerometers. It employs a feedback capacitance and a combination of switches to have the input parasitic capacitance and the offset voltage canceled. The raised current IDS of the input differential pair in the first stage is used to help reduce sharply the total low-frequency noises without increasing the complexity of the proposed circuit. The simulation result of the proposed circuit shows that an average 60% noise reduction at low frequencies has been achieved when the current in the current source of the first stage is raised six times the original. The root mean square equivalent input noise voltage is about 6.1nV/rtHz@1kHz. The experimental result shows that the capacitance resolution of the whole readout circuit is 10aF/rtHz@1kHz.