Growth and fabrication of InGaAs/InAlAs HEMTs on bonded-and-etch-back InP-on-Si

Abstract

InGaAs/InAlAs HEMTs fabricated on bonded-and-etched-back InP-on-Si substrates are reported. The process involves depositing SiO/sub 2/ on both the Si and InP substrates. The wafers are then contacted and bonded in a furnace at low temperature. Defects in the bond can be minimized by bonding in a particle-free environment. After bonding to a Si substrate, the InP wafer is thinned to <10 mu m and a strain-relief grid is etched through the InP to the SiO/sub 2/ layer. For fabrication of the HEMT, a standard processing sequence of mesa isolation, ohmic-contacts formation, gate-metal deposition and overlay was used. A maximum transconductance of 180 mS/mm was measured for a 1.2- mu m-gate-length device.<>