Improving the accuracy of on-chip parasitic extraction

Abstract

The rule-based layout parameter extraction (LPE) tools are most often used to extract the full-chip parasitics, but their accuracy strongly depends on how the capacitance models are specified. This paper shows that the generation of accurate capacitance models can be automated with thousands of field-solver simulations and nonlinear regression. The fundamental limitations of LPE tools are discussed. Finally, a 3D Monte-Carlo field solver is used to validate and further improve the LPE results.