A 101 dB Dynamic Range Delta-Sigma Modulator Using Modified Feed-Forward Architecture for Audio Application

Jun-Young Kil, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, G. Ahn
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Abstract

This paper presents a second-order delta-sigma modulator for audio applications. It uses modified feed-forward (FF) architecture that simplifies the switched-capacitor network of an analog adder in front of the quantizer. The modulator utilizes correlated-double-sampling (CDS) technique to attenuate flicker noise of the op-amp in the first integrator. The prototype analog-to-digital converter (ADC) is fabricated in a 0.18 µm CMOS process with an active die area of 0.119 mm2. It achieves a dynamic range (DR) of 101dB, a peak signal-to-noise ratio (SNR) of 97.7 dB and a peak signal-to-noise and distortion ratio (SNDR) of 91.5 dB in a 24kHz signal bandwidth while consuming 1.55 mW from a 1.8 V power supply.
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用于音频应用的改进前馈结构的101 dB动态范围Delta-Sigma调制器
本文提出了一种用于音频应用的二阶δ - σ调制器。它采用改进的前馈(FF)结构,简化了量化器前模拟加法器的开关电容网络。该调制器利用相关双采样(CDS)技术来衰减第一积分器运放的闪烁噪声。原型模数转换器(ADC)采用0.18 μ m CMOS工艺制造,有源芯片面积为0.119 mm2。在24kHz信号带宽下,其动态范围(DR)为101dB,峰值信噪比(SNR)为97.7 dB,峰值信噪比和失真比(SNDR)为91.5 dB,功耗为1.55 mW,电源电压为1.8 V。
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